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参数资料
| 型号： | LTC2941IDCB-1#TRMPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO6 |
| 封装： | 2 X 3 MM, LEAD FREE, PLASTIC, MO-229TBD, DFN-6 |
| 文件页数： | 2/16页 |
| 文件大小： | 206K |
| 代理商： | LTC2941IDCB-1#TRMPBF |
LTC2941-1
0
29411f
applicaTions inFormaTion
The default value after power up is M = 128 = 27 (B[5:3]
= 111). The maximum battery capacity supported within
the prescaler range is 5.5Ah with M = 128. See the section
Extending Coulomb Counter Range if battery capacity is
higher.
Depending on the choice of prescaler factor M, the charge
LSB of the accumulated charge register becomes:
q
mAh
M
LSB = 0 085
128
.
Note that the internal digital resolution of the coulomb
counter is higher than indicated by qLSB. The internal
charge resolution is typically 299As.
VBAT Alert B[7:6]
The VBAT alert function allows the LTC2941-1 to monitor
the voltage at SENSE–. If enabled, a drop of the voltage
at the SENSE– pin below a preset threshold is detected
and bit A[1] in the status register is set. If the alert mode
is enabled by setting B[2] to one, an alert is generated at
the AL/CC pin. The threshold for the VBAT alert function
is selectable according to Table 3.
Battery voltage is measured at the internal bond pads
connected to SENSE–, hence, the current flowing through
the combined pin and bond wire slightly shifts the battery
alert threshold levels. For the full-scale current of ±1A at
roomtemperature,thisshiftistypically±9mV,whichcanbe
ignoredformostapplications.TheVBATalertthresholdsare
specified with zero current through the sense resistor.
Accumulated Charge Register (C,D)
The coulomb counter of the LTC2941-1 integrates current
through its internal sense resistor over time. The result of
this charge integration is stored in the 16-bit accumulated
charge register (registers C, D). The amount of charge for
a given register contents (C[7:0]D[7:0]) and prescaler
setting M can be calculated by:
Q
mAh
M
C
D
=
+
(
)
0 085
128
256
.
The ACR should be read in a single I2C Read transaction
(see Figure 8). If C and D are read in individual single-byte
transactions, each with a STOP condition, the register
may change between the first and the second transaction
due to coulomb count events, causing erroneous charge
readings.
As the LTC2941-1 does not know the actual battery status
at power-up, the accumulated charge register (ACR) is set
to mid-scale (7FFFh). If the host knows the status of the
battery, the accumulated charge (C[7:0]D[7:0]) can be
either programmed to the correct value via I2C or it can be
set after charging to FFFFh (full) by pulling the AL/CC pin
high if charge complete mode is enabled via bits B[2:1]. In
this case, FFFFh represents a fully charged battery. If the
actual battery capacity is smaller, the host can subtract the
excess charge whenever doing the charge calculation, and
set the low charge threshold (registers G, H) to the value
representing an empty battery. This procedure essentially
shifts the zero point of the scale upwards. Before writing
the accumulated charge registers, the analog section
should be shut down by setting B[0] to 1.
Threshold Registers (E, F), (G, H)
For battery charge, the LTC2941-1 features a high and a
low threshold register. At power-up the high threshold is
set to FFFFh while the low threshold is set to 0000h. Both
thresholds can be programmed to a desired value via I2C.
As soon as the accumulated charge exceeds the high
threshold or falls below the low threshold, the LTC2941-1
sets the corresponding flag in the status register and pulls
the AL/CC pin low if alert mode is enabled.
I2C Protocol
The LTC2941-1 uses an I2C/SMBus compatible 2-wire
open-drain interface supporting multiple devices and
masters on a single bus. The connected devices can only
pull the bus wires low and they never drive the bus high.
The bus wires should be externally connected to a posi-
tive supply voltage via a current source or pull-up resistor.
When the bus is idle, both SDA and SCL are high. Data on
the I2C-bus can be transferred at rates of up to 100kbit/s
in standard mode and up to 400kbit/s in fast mode.
Each device on the I2C/SMbus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
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