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参数资料
| 型号： | LTC2941IDCB#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC FUEL/GAS GAUGE LI-ION 6DFN |
| 标准包装： | 500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 供应商设备封装： | 6-DFN-EP（2x3） |
| 包装： | 带卷 (TR) |
| 配用： | DC1496A-A-ND - BOARD EVAL LTC2941 |
LTC2941
APPLICATIONS INFORMATION
SDA
a6 - a0
b7 - b0
b7 - b0
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
2941 F04
Figure 4. Data Transfer Over I 2 C or SMBus
START and STOP Conditions
When the bus is idle, both SCL and SDA must be HIGH. A
bus master signals the beginning of a transmission with a
START condition by transitioning SDA from HIGH to LOW
while SCL is HIGH. When the master has ?nished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is then free for another transmission. When the
bus is in use, it stays busy if a repeated START (Sr) is
generated instead of a STOP condition. The repeated START
(Sr) conditions are functionally identical to the START (S).
Data Transmission
After a START condition, the I 2 C bus is considered busy
and data transfer begins between a master and a slave. As
data is transferred over I 2 C in groups of nine bits (eight
data bits followed by an acknowledge bit), each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an acknowledge (ACK) by pulling SDA LOW or
leaves SDA HIGH to indicate a not-acknowledge (NACK)
condition. Change of data state can only happen while
SCL is LOW.
Write Protocol
The master begins communication with a START condi-
tion followed by the seven bit slave address 1100100
and the R/ W bit set to zero, as shown in Figure 5. The
LTC2941 acknowledges this by pulling SDA LOW and
then the master sends a command byte which indicates
which internal register the master is to write. The LTC2941
acknowledges and then latches the command byte into
its internal register address pointer. The master delivers
the data byte, the LTC2941 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
master continues by sending a second data byte instead
of a STOP, the LTC2941 acknowledges again, increments
its address pointer and latches the second data byte in
the following register, as shown in Figure 6.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/ W bit set to zero, as shown in Figure 7. The LTC2941
acknowledges and then the master sends a command
byte which indicates which internal register the master is
to read. The LTC2941 acknowledges and then latches the
command byte into its internal register address pointer.
The master then sends a repeated START condition fol-
lowed by the same seven bit address with the R/ W bit
now set to one. The LTC2941 acknowledges and sends
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. If
the master acknowledges the transmitted data byte, the
LTC2941 increments its address pointer and sends the
contents of the following register, as shown in Figure 8.
2941fa
11
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