参数资料
型号: LTC3103EDD#PBF
厂商: Linear Technology
文件页数: 12/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.3A 10DFN
标准包装: 121
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 13.8 V
输入电压: 2.5 V ~ 15 V
PWM 型: 电流模式,混合
频率 - 开关: 1.2MHz
电流 - 输出: 300mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
LTC3103
APPLICATIONS INFORMATION
Table 2. Representative Inductor Selection
MAX DC
VALUE DCR CURRENT
PART NUMBER (μH) (Ω) (A)
Coilcraft
EPL3015 6.8 0.19 1.00
LPS3314 10 0.33 0.70
LPS4018 15 0.26 1.12
Cooper-Bussman
SD3114 6.8 0.30 0.98
SD3118 10 0.3 0.75
Murata
LQH3NPN 6.8 0.20 1.25
LQH44PN 10 0.16 1.10
Sumida
CDRH3D16 6.8 0.17 0.73
CDRH3D16 10 0.21 0.55
Taiyo-Yuden
CBC3225 6.8 0.16 0.93
NR3015 10 0.23 0.70
NR4018 15 0.30 0.65
Würth
744029006 6.8 0.25 0.95
744031006 6.8 0.16 0.85
744031100 10 0.19 0.74
SIZE (MM)
W × L × H
3.0 × 3.0 × 1.5
3.3 × 3.3 × 1.3
4.0 × 4.0 × 1.8
3.1 × 3.1 × 1.4
3.2 × 3.2 × 1.8
3.0 × 3.0 × 1.4
4.0 × 4.0 × 1.7
3.8 × 3.8 × 1.8
3.8 × 3.8 × 1.8
3.2 × 2.5 × 2.5
3.0 × 3.0 × 1.5
4.0 × 4.0 × 1.8
2.8 × 2.8 × 1.4
3.8 × 3.8 × 1.7
3.8 × 3.8 × 1.7
the point where switching delay and the high frequency
parasitic poles of the error amplifier will degrade the
phase margin. In addition, the wider bandwidth produced
by a small output capacitor will make the loop more sus-
ceptible to switching noise. At the other extreme, if the
output capacitor is too large, the crossover frequency
can decrease too far below the compensation zero and
also lead to degraded phase margin. Table 3 provides a
guideline for the range of allowable values of low ESR
output capacitors assuming a feedforward capacitor is
used. See the Output Voltage Programming section for
details on selecting a feedforward capacitor. Larger value
output capacitors can be accommodated provided they
have sufficient ESR to stabilize the loop, or by increasing
the value of the feedforward capacitor in parallel with the
upper resistor divider resistor.
In Burst Mode operation, the output capacitor stores energy
to satisfy the load current when the LTC3103 is in a low
current sleep state between the burst pulses. It can take
several cycles to respond to a large load step during a sleep
period. If large transient load currents are required then
a larger capacitor can be used at the output to minimize
output voltage droop until the part transitions from Burst
Mode operation to continuous mode operation.
744031100 15 0.26 0.62 3.8 × 3.8 × 1.7
Panasonic
ELLVGG6R8N 6.8 0.23 1.00 3.0 × 3.0 × 1.5
ELL4LG100MA 10 0.20 0.80 3.8 × 3.8 × 1.8
TDK
VLF3012 6.8 0.18 0.78 3.0 × 2.8 × 1.2
VLC4018 10 0.16 0.85 4.0 × 4.0 × 1.8
Output Capacitor Selection
A low ESR output capacitor should be utilized at the buck
output in order to minimize voltage ripple. Multilayer ce-
ramic capacitors are an excellent choice as they have low
ESR and are available in small footprints. In addition to
controlling the output ripple magnitude, the value of the
output capacitor also sets the loop crossover frequency
and therefore can impact loop stability. There is both a
minimum and maximum capacitance value required to
ensure stability of the loop. If the output capacitance is
too small, the loop crossover frequency will increase to
Note that even X5R and X7R type ceramic capacitors have
a DC bias effect which reduces their capacitance when a
DC voltage is applied. It is not uncommon for capacitors
offered in the smallest case sizes to lose more than 50%
of their capacitance when operated near their rated volt-
age. As a result it is sometimes necessary to use a larger
capacitance value or use a higher voltage rating in order to
realize the intended capacitance value. Consult the manu-
facturer’s data for the capacitor you select to be assured
of having the necessary capacitance in your application.
Table 3. Recommended Output Capacitor Limits
OUTPUT VOLTAGE (V) C MIN (μF) C MAX (μF)
0.8 22.0 220
1.2 15.0 220
2.0 12.0 100
2.7 6.8 68
3.3 4.7 47
5.0 4.7 47
3103f
12
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