参数资料
型号: LTC3105EDD#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PDSO10
封装: 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10
文件页数: 18/18页
文件大小: 1913K
代理商: LTC3105EDD#PBF
LTC3105
9
3105fa
3105 F01
OUTPUT
VOL
TAGE
INDUCTOR
CURRENT
TIME
NORMAL OPERATION
LDO IN
REGULATION
1.4V
VOUT SYNCHRONOUS
RECTIFIER ENABLED
VAUX
VOUT
VOUT IN
REGULATION
VOUT = VAUX
START-UP MODE
VLDO
above VAUX, an internal switch is enabled to connect the
two outputs together.
If VIN is greater than the voltage on the driven output (VOUT
or VAUX), or the driven output is less than 1.2V (typical),
the synchronous rectifiers are disabled. With the synchro-
nous rectifiers disabled, the converter operates in critical
conduction mode. In this mode, the N-channel MOSFET
between SW and GND is enabled and remains on until the
inductor current reaches the peak current limit. It is then
disabled and the inductor current discharges completely
before the cycle is repeated.
When the output voltage is greater than the input voltage
andgreaterthan1.2V,thesynchronousrectifierisenabled.
In this mode, the N-channel MOSFET between SW and
GND is enabled until the inductor current reaches the peak
current limit. Once current limit is reached, the N-channel
MOSFETturnsoffandtheP-channelMOSFETbetweenSW
and the driven output is enabled. This switch remains on
until the inductor current drops below the valley current
limit and the cycle is repeated.
Figure 1. Typical Converter Start-Up Sequence
When VOUT reaches the regulation point, the N- and P-
channel MOSFETs connected to the SW pin are disabled
and the converter enters sleep.
Auxiliary LDO
The integrated LDO provides a regulated 6mA rail to
power microcontrollers and external sensors. When the
input voltage is above the minimum of 225mV, the LDO is
powered from the AUX output allowing the LDO to attain
regulation while the main output is still charging. The LDO
has a 12mA current limit and an internal 1ms soft-start
to eliminate inrush currents. The LDO output voltage is
set by the FBLDO pin. If a resistor divider is connected
to this pin, the ratio of the resistors determines the LDO
output voltage. If the FBLDO pin is connected directly to
GND, the LDO will use a 2MΩ internal divider network to
program a 2.2V nominal output voltage. The LDO should
be programmed for an output voltage less than the pro-
grammed VOUT.
OPERATION
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