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参数资料
| 型号： | LTC3226EUD#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHED CAPACITOR REGULATOR, PQCC16 |
| 封装： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16 |
| 文件页数： | 14/16页 |
| 文件大小： | 431K |
| 代理商： | LTC3226EUD#PBF |
LTC3226
7
3226f
PIN FUNCTIONS
VOUT (Pin 1): Voltage Output. This pin is used to provide
power to an external load from either the primary input
supply (VIN) or the supercapacitor (CPO) if the primary
input supply is not available. VOUT should be bypassed
with a low ESR ceramic capacitor of at least 47F capaci-
tance to GND.
PFO (Pin 2): Open-Drain Power-Fail Status Output. This
pin is pulled to ground by an internal N-channel MOSFET
when the PFI input is below 1.2V. Once the PFI input re-
covers, this pin becomes high impedance.
PFI (Pin 3): Power-Fail Input. High impedance input to
an accurate comparator with a 1.2V falling threshold and
20mV hysteresis. This pin controls the state of the PFO
output pin and the operating mode of the LTC3226.
LDO_FB (Pin 4): Internal LDO Feedback Pin. The voltage
on this pin is compared to the internal reference voltage
(0.8V) by the error amplifier to keep the output in regula-
tion.AnexternalresistordividerisrequiredbetweenVOUT,
LDO_FB and GND to program the LDO output voltage. See
the Applications Information section.
GATE (Pin 5): External FET Gate Pin. This pin is driven
by an internal ideal diode controller to regulate VOUT to
15mV below VIN.
RST_FB (Pin 6): Reset Comparator Input. High imped-
ance input to an accurate comparator with a 0.74V falling
threshold and 20mV hysteresis. This pin controls the
state of the RST output pin. An external resistor divider
is required between VOUT, RST_FB and GND. It can be
the same resistor divider as the LDO_FB divider. See the
Applications Information section.
RST (Pin 7): Open-Drain Status Output of the RESET
Comparator. This pin is pulled to ground by an internal
N-channelMOSFETwhenevertheRST_FBpinvoltagefalls
below 0.74V. Once the RST_FB pin voltage recovers, the
pin becomes high impedance after a 290ms delay indicat-
ing that VOUT is within 7.5% of its programmed value.
EN_CHG (Pin 8): Enable Pin for the Charge Pump Super-
capacitor Charger with an Internal Pull-Up. Tie this pin to
a voltage below 0.4V to disable the internal charge pump.
PROG (Pin 9): Charger Input Current Limit Programming
Pin. A resistor connected between this pin and GND sets
the input current limit for the charger. See the Applications
Information section.
CPO_FB (Pin 10): Feedback Pin for the Charge Pump. The
voltage on this pin is compared to the internal reference
voltage (1.2V) to keep the charge pump output CPO in
regulation.Anexternalresistordividerisrequiredbetween
CPO, CPO_FB and GND to program the CPO output volt-
age. See the Applications Information section.
CAPGOOD (Pin 11): Open-Drain Status Output of the
CPO Voltage. This pin is pulled to ground by an internal
N-channel MOSFET until CPO_FB pin reaches 1.11V. Once
the CPO_FB pin exceeds 1.11V, this pin becomes high
impedance indicating that the CPO voltage is within 7.5%
of its target value.
C– (Pin 12): Internal Charge Pump Flying Capacitor
Negative Terminal.
VIN(Pin13):PrimaryInputSupply.Thispinsuppliespower
to the VOUT pin through an external P-channel MOSFET
and also to the supercapacitors attached to the CPO and
VMID pins. VIN should be bypassed to GND with a low
ESR ceramic capacitor of at least 2.2μF depending on the
load transient.
VMID (Pin 14): Midpoint of Two Series Supercapacitors.
C+(Pin15):InternalChargePumpFlyingCapacitorPositive
Terminal. A 1μF to 10μF X5R or X7R ceramic capacitor
should be connected from C+ to C–.
CPO (Pin 16): Backup Supply Pin. Connect CPO to the top
plate of the top supercapacitor. This pin receives power
from VIN through an internal charge pump doubler and
supplies power to VOUT through an internal LDO when the
primary input supply has failed.
GND (Exposed Pad Pin 17): Ground. The exposed pad
should be connected to a continuous ground plane on
the second layer of the printed circuit board by several
vias directly under the part to achieve optimal thermal
performance.
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