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参数资料
| 型号： | LTC3240EDC-3.3#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG 3.3V 6DFN |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压），切换电容（充电泵） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 3.3V |
| 输入电压： | 1.8 V ~ 5.5 V |
| PWM 型： | Burst Mode? |
| 频率 - 开关： | 1.2MHz |
| 电流 - 输出： | 150mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 包装： | 剪切带 (CT) |
| 供应商设备封装： | 6-DFN-EP（2x2） |
| 产品目录页面： | 1339 (CN2011-ZH PDF) |
| 其它名称： | LTC3240EDC-3.3#TRMPBFCT |
LTC3240-3.3/LTC3240-2.5
APPLICATIO S I FOR ATIO
to additional switch resistance. However, for very light
load applications, the above expression can be used as a
guideline in determining a starting capacitor value.
C IN
1 μ F
0603
GND
SHDN
Ceramic Capacitors
Ceramic capacitors of different materials lose their ca-
V IN
V OUT
C –
C FLY
1 μ F
pacitance with higher temperature and voltage at differ-
ent rates. For example, a capacitor made of X5R or X7R
C OUT
4.7 μ F
0603
C +
0603
material will retain most of its capacitance from –40°C
to 85°C whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range. Z5U and Y5V
capacitors may also have a poor voltage coef?cient causing
them to lose 60% or more of their capacitance when the
rated voltage is applied. Therefore when comparing dif-
ferent capacitors, it is often more appropriate to compare
the amount of achievable capacitance for a given case size
rather than discussing the speci?ed capacitance value. For
example, a 4.7μF 10V Y5V ceramic capacitor in a 0805
case only retains 25% of its rated capacitance over tem-
perature with a 3.3V bias, while a 4.7μF 10V X5R ceramic
capacitor will retain 80% of its rated capacitance over the
same conditions. The capacitor manufacturer’s data sheet
should be consulted to ensure the desired capacitance at
all temperatures and voltages.
Below is a list of ceramic capacitor manufacturers and
how to contact them:
3240 F04
Figure 4. Recommended Layout
Thermal Management
For higher input voltages and maximum output current,
there can be substantial power dissipation in the LTC3240.
If the junction temperature increases above approximately
160°C, the thermal shutdown circuitry will automatically
deactivate the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board is
recommended. Connecting GND (Pin 1) and the Exposed
Pad of the DFN package to a ground plane under the device
on two layers of the PC board can reduce the thermal
resistance of the package and PC board considerably.
Derating Power at High Temperatures
AVX
Kemet
Murata
Taiyo Yuden
Vishay
TDK
www.avxcorp.com
www.kemet.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.component.tdk.com
To prevent an overtemperature condition in high power
applications, Figure 5 should be used to determine the
maximum combination of ambient temperature and power
dissipation.
The power dissipated in the LTC3240 should always fall
under the line shown for a given ambient temperature.
The power dissipation of the LTC3240 in step-up mode
Layout Considerations
Due to the high switching frequency and high transient
currents produced by LTC3240, careful board layout is
necessary for optimum performance. A true ground plane
and short connections to all the external capacitors will
is given by the expression:
P D = (2V IN – V OUT ) ? I OUT
The power dissipation in step-down mode is given by:
P D = (V IN – V OUT ) ? I OUT
improve performance and ensure proper regulation under
all conditions. Figure 4 shows an example layout for the
LTC3240.
3240fb
10
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