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参数资料
| 型号： | LTC3240EDC-3.3#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG 3.3V 6DFN |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压），切换电容（充电泵） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 3.3V |
| 输入电压： | 1.8 V ~ 5.5 V |
| PWM 型： | Burst Mode? |
| 频率 - 开关： | 1.2MHz |
| 电流 - 输出： | 150mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 包装： | 剪切带 (CT) |
| 供应商设备封装： | 6-DFN-EP（2x2） |
| 产品目录页面： | 1339 (CN2011-ZH PDF) |
| 其它名称： | LTC3240EDC-3.3#TRMPBFCT |
LTC3240-3.3/LTC3240-2.5
APPLICATIO S I FOR ATIO
3.0
2.5
2.0
1.5
1.0
0.5
θ JA = 80 ° C/W
RECOMMENDED
OPERATION
T J = 125 ° C
THERMAL
SHUTDOWN
T J = 160 ° C
This derating curve assumes a maximum thermal resis-
tance, θ JA , of 80°C/W for the 2 × 2 DFN package. This can
be achieved from a printed circuit board layout with a solid
ground plane and a good connection to the ground pins of
LTC3240 and the Exposed Pad of the DFN package.
It is recommended that the LTC3240 be operated in the
region corresponding to T J ≤ 125°C for continuous opera-
tion as shown in Figure 5. Short term operation may be
acceptable for 125°C ≤ T J ≤ 160°C but long term operation
0
– 50 – 25
0 25 50 75 100 125 150
AMBIENT TEMPERATURE ( ° C)
LT3240 F05
in this region should be avoided as it may reduce the life of
the part or cause degraded performance. For T J ≥ 160°C,
the part will be in thermal shutdown.
Figure 5. Maximum Power Dissipation vs Ambient Temperature
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
R = 0.115
TYP
0.38 ± 0.05
0.675 ± 0.05
0.56 ± 0.05
(2 SIDES)
4
6
1.15 ± 0.05 0.61 ± 0.05
3
1
2.50 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.42 ± 0.05
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
2.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ± 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3240fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
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