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参数资料
| 型号： | LTC3406ES5-1.8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 1.8V TSOT23-5 |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 1.8V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.5MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | TSOT-23-5 |
LTC3406
LTC3406-1.5/LTC3406-1.8
APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3406 circuits: V IN quiescent current and I 2 R
losses. The V IN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I 2 R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 4.
2. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and external inductor R L . In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
1
0.1
0.01
0.001
0.0001
0.00001
V OUT = 1.2V
V OUT = 1.5V
V OUT = 1.8V
V OUT = 2.5V
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I 2 R losses, simply add R SW to
R L and multiply the result by the square of the average
output current.
Other losses including C IN and C OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
0.1
1
10 100
LOAD CURRENT (mA)
1000
In most applications the LTC3406 does not dissipate
3406 F04
Figure 4. Power Lost vs Load Current
1. The V IN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V IN to ground. The resulting
dQ/dt is the current out of V IN that is typically larger than
the DC bias current. In continuous mode, I GATECHG =
f(Q T + Q B ) where Q T and Q B are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V IN and thus
their effects will be more pronounced at higher supply
voltages.
much heat due to its high efficiency. But, in applications
where the LTC3406 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150 ° C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3406 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T R = (P D )( θ JA )
where P D is the power dissipated by the regulator and θ JA
is the thermal resistance from the junction of the die to the
ambient temperature.
3406fa
10
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