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参数资料
| 型号： | LTC3409IDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.6A 8DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.62 V ~ 5.5 V |
| 输入电压： | 1.6 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.7MHz ~ 2.6MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN-EP（3x3） |
LTC3409
APPLICATIONS INFORMATION
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (R DS(ON) ).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V OUT immediately shifts by an amount
equal to (ΔI LOAD ? ESR), where ESR is the effective series
resistance of C OUT . ΔI LOAD also begins to charge or dis-
charge C OUT , which generates a feedback error signal. The
regulator loop then acts to return V OUT to its steady state
value. During this recovery time V OUT can be monitored
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C OUT , causing a rapid drop in V OUT . No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 ? C LOAD ). Thus, a 10μF capacitor charging to 3.3V
would require a 250μs rise time, limiting the charging
2. Are the C OUT and L1 closely connected? The (–) plate of
C OUT returns current to GND and the (–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals V FB should be routed away from noisy compo-
nents and traces, such as the SW line (Pins 6), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C IN and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
C IN or C OUT .
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V IN or GND.
V IN
C IN
current to about 130mA.
V IN
V IN
Board Layout Considerations
LTC3409
RUN SYNC
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
V FB MODE
SW
SGND GND
L1
C1
V OUT
the LTC3409. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
C OUT
your layout.
1. Does the capacitor C IN connect to the power V IN
(Pins 3, 4) and GND (Exposed Pad) as close as pos-
sible? This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
R2
R1
Figure 3
3409 F03
3409fc
13
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