参数资料
型号: LTC3411AEMS#TRPBF
厂商: Linear Technology
文件页数: 17/22页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 10MSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.5MHz
电流 - 输出: 1.25A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
LTC3411A
APPLICATIONS INFORMATION
C OUT ≈ 2.5
= 25μF
For cost reasons, a ceramic capacitor will be used. C OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
1.25A
1MHz ? (5% ? 2.5V)
The closest standard value is 22μF. Since the output
impedance of a Li-Ion battery is very low, C IN is typically
10μF. In noisy environments, decoupling SV IN from PV IN
with an R6/C8 filter of 1Ω/0.1μF may help, but is typically
not needed.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.8V feedback voltage makes R1~400k. A close
standard 1% resistor value is 412k. Then R2 is 887k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3411A is with a 12.1kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
The circuit on page 1 of this data sheet shows the complete
schematic for this design example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
C IN
V IN
the LTC3411A. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout:
1. Does the capacitor C IN connect to the power V IN (Pin 6)
and power GND (Pin 5) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C OUT and L1 closely connected? The (–) plate of
C OUT returns current to PGND and the (–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground line terminated
near SGND (Pin 3). The feedback signal V FB should be
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C IN , the compensation capacitor C C and
C ITH and all the resistors R1, R2, R T , and R C should be
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PV IN , PGND, SV IN or SGND.
PGOOD
R5
PV IN
SV IN
PGOOD
PGND
SW
LTC3411A SGND
L1
V IN
C OUT
V OUT
C4
R2
R1
R C
C C
V FB
I TH
C ITH
SYNC/MODE
SHDN/R T
PS
BM
R T
3411A F07
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 7. LTC3411A Layout Diagram (See Board Layout Checklist)
3411afc
For more information www.linear.com/LTC3411A
17
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