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参数资料
| 型号： | LTC3414MPFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 20TSSOP |
| 标准包装： | 76 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.25 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 20-TSSOP-EP |
LTC3414
APPLICATIO S I FOR ATIO
The V IN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I 2 R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V IN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is the current out
of V IN that is typically larger than the DC bias current. In
continuous mode, I GATECHG = f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V IN ; thus, their effects will be more pro-
nounced at higher supply voltages.
2. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and external inductor R L . In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R DS(ON) and the duty cycle (DC) as follows:
R SW = (R DS(ON) TOP)(DC) + (R DS(ON) BOT)(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I 2 R losses, simply add R SW to R L and
multiply the result by the square of the average output
current.
Other losses including C IN and C OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3414 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3414 is running at
high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150 ° C, both power switches will be turned off and the SW
node will become high impedance.
To avoid the LTC3414 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
t r = (P D )( θ JA )
where P D is the power dissipated by the regulator and θ JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the θ JA is 38 ° C/W.
The junction temperature, T J , is given by:
T J = T A + t r
where T A is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R DS(ON) ).
To maximize the thermal performance of the LTC3414, the
exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V OUT immediately shifts by an
amount equal to Δ I LOAD(ESR) , where ESR is the effective
series resistance of C OUT . Δ I LOAD also begins to charge or
discharge C OUT generating a feedback error signal used by
the regulator to return V OUT to its steady-state value.
During this recovery time, V OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I TH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
3414fb
11
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