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参数资料
| 型号： | LTC3417AIFE-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ DL 20TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.25 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.5MHz，600kHz ~ 4MHz |
| 电流 - 输出： | 1A，1.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-TSSOP-EP |
LTC3417A-2
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417A-2. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1. Does the capacitor C IN connect to the power V IN1
(Pin 2), V IN2 (Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
to split C IN into two capacitors. This capacitor provides
the AC current to the internal power MOSFETs and
their drivers.
2. Are the C OUT1 , L 1 and C OUT2 , L 2 closely connected? The
(–) plate of C OUT1 returns current to PGND1, and the
(–) plate of C OUT2 returns current to the PGND2/GNDD
and the (–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT1 and a ground line ter-
minated near GNDA. The resistor divider, R3 and R4,
V IN
must be connected between the (+) plate of C OUT2 and
a ground line terminated near GNDA. The feedback
signals V FB1 and V FB2 should be routed away from noise
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C IN , the compensation capacitors
C C1 , C C2 , C ITH1 and C ITH2 and all resistors R1, R2, R3,
R4, R ITH1 and R ITH2 should be routed away from the
SW traces and the inductors L1 and L2.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the PGND2/GNDD
pin.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
C OUT2
C IN
10μF
C IN2
0.1μF
V IN2
PGND2/
EXPOSED PAD
GNDA
V IN1
PGND1
C IN1
0.1μF
C OUT1
L2
L1
V OUT2
C C2
R3
SW2
V FB2
LTC3417A-2
SW1
V FB1
R1
C C1
V OUT1
R4
R2
STAR TO
GNDA
R ITH2
I TH2
I TH1
R ITH1
STAR TO
GNDA
V IN
C ITH2
R8
POR
FREQ
R7
C ITH1
RUN2
PHASE
RUN1
SYNC/MODE
V IN
GNDD
3417A-2 F05
Figure 5. Layout Guideline
3417a2fa
18
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