参数资料
型号: LTC3418EUHF#PBF
厂商: Linear Technology
文件页数: 11/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 8A 38QFN
标准包装: 52
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 8A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 38-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 38-QFN(5x7)
产品目录页面: 1334 (CN2011-ZH PDF)
LTC3418
APPLICATIONS INFORMATION
V OUT
pin to ground. This sets I BURST to 0A. In this condition, the
V FB
LTC3418
R2
R1
peak inductor current is limited by the minimum on-time
of the current comparator; and the lowest output voltage
ripple is achieved while still operating discontinuously.
During very light output loads, pulse skipping allows only
SGND
3418 F01
a few switching cycles to be skipped while maintaining
the output voltage in regulation.
Figure 1. Setting the Output Voltage
Voltage Tracking
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V IN by
1V, Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak induc-
tor current, I BURST , for each switching cycle. A graph show-
ing the relationship between the minimum peak inductor
current and the voltage on the SYNC/MODE pin can be
found in the Typical Performance Characteristics section.
In the graph, V BURST is the voltage on the SYNC/MODE
pin. I BURST can only be programmed in the range of 0A
to 10A. For values of V BURST less than 0.4V, I BURST is set
at 0A. As the output load current drops, the peak inductor
currents decrease to keep the output voltage in regulation.
When the output load current demands a peak inductor
current that is less than I BURST , the burst clamp will force
the peak inductor current to remain equal to I BURST regard-
less of further reductions in the load current. Since the
The LTC3418 allows the user to program how its output
voltage ramps during start-up by means of the TRACK
pin. Through this pin, the output voltage can be set up to
either track coincidentally or ratiometrically follow another
output voltage as shown in Figure 2. If the voltage on the
TRACK pin is less than 0.8V, voltage tracking is enabled.
During voltage tracking, the output voltage regulates to
the tracking voltage through a resistor divider network.
V OUT2
V OUT1
average inductor current is greater than the output load
current, the voltage on the I TH pin will decrease. When
TIME
3418 F02a
the I TH voltage drops to 350mV, sleep mode is enabled
in which both power MOSFETs are shut off and switching
action is discontinued to minimize power consumption.
All circuitry is turned back on and the power MOSFETs
begin switching again when the output voltage drops out
of regulation. The value for I BURST is determined by the
desired amount of output voltage ripple. As the value of
I BURST increases, the sleep period between pulses and the
output voltage ripple increase. The burst clamp voltage,
V BURST , can be set by a resistor divider from the V FB pin
to the SGND pin as shown in the Typical Application on
the front page of this data sheet.
Figure 2a. Coincident Tracking
V OUT2
V OUT1
Pulse skipping, which is a compromise between low output
TIME
3418 F02a
voltage ripple and ef ?ciency during low load current opera-
Figure 2b. Ratiometric Sequencing
tion, can be implemented by connecting the SYNC/MODE
3418fb
11
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