参数资料
型号: LTC3418EUHF#TRPBF
厂商: Linear Technology
文件页数: 7/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 8A 38QFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 8A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 38-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 38-QFN(5x7)
LTC3418
OPERATION
Main Control Loop
The LTC3418 is a monolithic, constant frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the I TH pin.
The error ampli?er adjusts the voltage on the I TH pin by
comparing the feedback signal from a resistor divider on
the V FB pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error ampli?er raises
the I TH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –8A for force continuous mode and 0A for
Burst Mode operation.
The operating frequency is externally set by an external
resistor connected between the R T pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous
Connecting the SYNC/MODE pin to SV IN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
ef ?cient than Burst Mode operation, but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0V to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases ef ?ciency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I TH pin drops. As the I TH voltage falls
below 350mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET
is held off while the load current is solely supplied by the
output capacitor. When the output voltage drops, the top
and bottom power MOSFETs begin switching to bring the
output back into regulation. This process repeats at a rate
that is dependent on the load demand.
Pulse skipping operation can be implemented by connect-
ing the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage
on the I TH pin until the I TH voltage drops below 400mV. At
this point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3418 can by synchronized
to an external clock connected to the SYNC/MODE pin.
The frequency of the external clock can be in the range
of 300kHz to 4MHz.
For this application, the oscillator timing resistor should
be chosen to correspond to a frequency that is 25% lower
than the synchronization frequency. During synchroniza-
tion, the burst clamp is set to 0V, and each switching cycle
begins at the falling edge of the clock signal.
3418fb
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