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参数资料
| 型号： | LTC3448EDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.6A 8DFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.2 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.5MHz ~ 2.25MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 8-DFN-EP（3x3） |
LTC3448
OPERATIO
(Refer to Functional Diagram)
the V OUT pin and both the main and synchronous switches
are turned off. The control loop is stabilized by the load
capacitor and requires a minimum value of 2 μ F. The
LTC3448 will change back to switching mode and turn off
the LDO when the load current exceeds approximately
11mA.
When MODE is connected to an intermediate voltage level
(i.e., V OUT ), this switchover is automatic. If MODE is pulled
high to V IN , the LDO remains on and the switcher off
regardless of the load current. The LDO is capable of
providing a maximum of approximately 15mA before the
load regulation will degrade to unacceptable levels. If
MODE is pulled to GND, the switcher remains on and the
LDO off regardless of the load current.
4.5
Some applications may be able to anticipate the transition
from high to low and low to high load currents. In these
cases it may be desirable to switch between modes by
controlling the MODE pin with a processor signal. In these
applications it is important that the MODE pin is pulled
high no earlier than 50 μ s after the RUN pin is pulled high.
This will ensure proper start-up of internal reference
circuitry.
The load current I LDO(ON) below which the switcher will
automatically turn off and the LDO turn on is independent
of the external capacitor, and to first order, independent
of supply and output voltage. There is an inverse relation-
ship between I LDO(ON) and the value of the inductor.
These dependencies are shown in Figures 2 and 3.
Automatic operation with inductor values below 1 μ H is
not recommended.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V OUT = 1.2V
V OUT = 1.5V
V OUT = 1.8V
At the low load currents at which the switcher to linear
regulator transition occurs, the switcher is operating in
pulse skipping mode. During each switching cycle in this
mode, while the synchronous switch (bottom MOSFET) is
on, the inductor current decays until the reverse current
comparator is triggered. At this occurrence, the bottom
MOSFET is turned off. Ideally, this occurs when the
0.5
0
2
3
4
V IN (V)
5
T A = 25 ° C
L = 2.2 μ H
6
inductor current is precisely zero. In reality, because of on-
chip delays, this current will be negative at higher output
voltages.
3448 F02
Figure 2. I LDO(ON) vs V IN , V OUT
The internal algorithm which controls the LDO turn-on
load current level makes certain assumptions about the
amount of charge transferred to the output on each
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V IN = 3.6V
V OUT = 1.5V
T A = 25 ° C
switching cycle. These assumptions are no longer met
when the inductor current begins to reverse. This causes
the load current at which the transition takes place to move
to lower levels at higher output voltages. For this reason
use of the LDO auto mode is not recommended for output
levels above 2V. For output voltages above 2V, the MODE
pin should be driven externally.
Short-Circuit Protection
0
0
2
4 6 8
INDUCTOR VALUE ( μ H)
10
12
When the output is shorted to ground, the main switch
cycle will be skipped, and the synchronous switch will
Figure 3. I LDO(ON) vs L OUT
3448 F03
remain on for a longer duration. This allows the inductor
current more time to decay, thereby preventing runaway.
3448f
8
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