参数资料
型号: LTC3533EDE#TRPBF
厂商: Linear Technology
文件页数: 6/16页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 14DFN
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.25 V
输入电压: 1.8 V ~ 5.5 V
PWM 型: Burst Mode?
频率 - 开关: 300kHz ~ 2MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 14-DFN-EP(4x3)
LTC3533
PIN FUNCTIONS
R T (Pin 1): Programs the Frequency of the Internal Oscil-
lator. Connect a resistor from R T to ground.
f(kHz) = 33,170/R T (k Ω )
BURST (Pin 2): Used to set the Automatic Burst Mode
Threshold. Connect a resistor and capacitor in parallel
from this pin to ground. See the Applications Information
section for component value selection. For manual control,
ground the pin to force Burst Mode operation, connect to
V IN to force ?xed frequency PWM mode.
SGND (Pin 3): Signal ground for the IC.
SW1 (Pin 4): Switch Pin where Internal Switches A and B
are Connected. Connect inductor from SW1 to SW2. An
optional Schottky diode can be connected from SW1 to
ground for a moderate ef?ciency improvement. Minimize
trace length to reduce EMI.
PGND1, PGND2 (Pins 5, 6): Power Ground for the Internal
NMOS Power Switches.
PV OUT (Pin 9): Output of the Synchronous Recti?er. A
?lter capacitor is placed from PV OUT to PGND. A ceramic
bypass capacitor is recommended as close to the PV OUT
and PGND pins as possible.
V IN (Pin 10): Input Supply Pin. Internal V CC for the IC.
PV IN (Pin 11): Power V IN Supply Pin. A 10μF ceramic
capacitor is recommended as close to the PV IN and PGND
pins as possible.
RUN/SS (Pin 12): Combined Enable and Soft-Start. Applied
voltage <0.4V shuts down the IC. Tie to >1.4V to enable
the IC and >1.6V to ensure the error amp is not clamped
from soft-start. An RC from the shutdown command signal
to this pin will provide a soft-start function by limiting the
rise time of V C
FB (Pin 13): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 1.8V to
5.25V. The feedback reference voltage is typically 1.22V.
SW2 (Pin 7): Switch Pin where Internal Switches C and
D are Connected. An optional Schottky diode can be
V OUT = 1 . 22 ?
R1 + R2
R 2
connected from SW2 to V OUT for a moderate ef?ciency
improvement. For applications with output voltages over
4.3V, this Schottky diode is required to ensure the SW2
pin does not exhibit excess voltage. Minimize trace length
to reduce EMI.
V OUT (Pin 8): Voltage Sensing Pin for PV OUT and Input
Supply Pin for Internal Circuitry Powered by PV OUT . A ?lter
capacitor is placed from V OUT to GND. A ceramic bypass
capacitor is recommended as close to the V OUT and GND
V C (Pin 14): Error Amp Output. An R-C network is con-
nected from this pin to FB for loop compensation. Refer
to “Closing the Feedback Loop” section for component
selection guidelines. During Burst Mode operation, V C is
internally connected to a hold circuit.
Exposed Pad (Pin 15): IC Substrate Ground. This pin must
be soldered to the PCB ground to provide both electrical
contact and a good thermal contact to the PCB.
pins as possible.
3533f
6
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