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| 型号： | LTC3539EDCB-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST SYNC ADJ 2A 8DFN |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.5 V ~ 5.25 V |
| 输入电压： | 0.5 V ~ 5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN（3x2） |
LTC3539/LTC3539-2
APPLICATIONS INFORMATION
V IN > V OUT Operation
The LTC3539 will maintain output voltage regulation even
when the input voltage is above the desired output. Note that
the efficiency and the maximum output current capability
are reduced. Refer to Typical Performance Characteristics.
Short-Circuit Protection
The LTC3539 output disconnect feature allows an output
short circuit while maintaining a maximum internally set
current limit. To reduce power dissipation under short-
circuit conditions, the peak switch current limit is reduced
to 1.4A (typical).
Schottky Diode
COMPONENT SELECTION
Inductor Selection
The LTC3539 can utilize small surface mount and chip
inductors due to the high switching frequency. Inductor
values between 3.3μH and 4.7μH for the LTC3539 and
between 1.5μH and 2.5μH for the LTC3539-2 are suitable
for most applications.* Larger values of inductance will
allow slightly greater output current capability (and lower
the Burst Mode threshold) by reducing the inductor ripple
current. However, increasing the inductance above 10μH
will increase size while providing little improvement in
output current capability.
The minimum inductance value is given by:
Although it is not required, adding a Schottky diode from
SW to V OUT will improve efficiency by about 2%. Note that
this defeats the output disconnect, V IN > V OUT operation
and short circuit protection features.
L >
Where:
V IN(MIN) ? (V OUT(MAX) ? V IN(MIN) )
Ripple ? V OUT(MAX) ? f
+
PCB LAYOUT GUIDELINES
The high speed operation of the LTC3539 demands careful
attention to board layout. A careless layout will result in
reduced performance. Figure 1 shows the recommended
component placement. A large ground pin copper area will
help to lower the die temperature. A multilayer board with
a separate ground plane is ideal.
LTC3539
SW 1 8 V OUT
PGND 2 7 MODE
MINIMIZE
GND 3 6 FB TRACE ON FB
AND SW
V IN 4 5 SHDN
V IN
MULTIPLE VIAS
TO GROUND PLANE
f = 1 for the LTC3539 or 2 for the LTC3539-2
Ripple = allowable inductor current ripple (Amps
peak-to-peak)
V IN(MIN) = minimum input voltage
V OUT(MAX) = maximum output voltage
The inductor current ripple is typically set for 20% to 40%
of the maximum inductor current. High frequency ferrite
core inductor materials improve efficiency by reducing
frequency dependent power losses compared to cheaper
powdered iron types. The inductor should have low ESR
(series resistance of the windings) to reduce the I 2 R power
losses, and must accommodate the peak inductor current
without saturating. Molded chokes and some chip induc-
tors usually do not have enough core area to support the
peak inductor current of 2.6A seen on the LTC3539. To
minimize radiated noise, use a shielded inductor. See Table
1 for suggested suppliers and representative components.
*Single cell applications (V IN < 1.6V) should use a 2.2μH inductor for the LTC3539
3539 F01
Figure 1. Recommended Component Placement for
Single Layer Board
35392fb
For more information www.linear.com/3539/3539-2
9
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