参数资料
型号: LTC3543EDCB#TRPBF
厂商: Linear Technology
文件页数: 12/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3543
APPLICATIONS INFORMATION
C IN and C OUT Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V OUT /V IN . To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
for use in switching power supplies. An excellent choice
is the AVX TPS series of surface mount tantalum. These
are specially constructed and tested for low ESR so they
give the lowest ESR for a given volume. Other capacitor
types include the Sanyo POSCAP, the Kemet T510 and T495
series, and the Sprague 593D and 595D series. Consult
the manufacturer for other speci?c recommendations.
C IN required I RMS ? I O(MAX) ?
[V OUT (V IN –V OUT )] 1 / 2
V IN
(2)
C1 Selection
When spread spectrum operation is enabled, the fre-
This formula has a maximum of V IN = 2V OUT , where I RMS
= I OUT /2. This simple worst-case condition is commonly
used for design because even signi?cant deviations do not
offer much relief. Note that the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of
life. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
than required. Always consult the manufacturer if there
are any questions.
The selection of C OUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for C OUT has been met, the RMS current rating
generally far exceeds the I RIPPLE(P-P) requirement. The
output ripple Δ V OUT is determined by:
quency of the LTC3543 is randomly varied over the
range of frequencies between 2MHz and 3MHz. In
this case, a capacitor should be connected between
the CAP pin and GND to smooth out the changes in fre-
quency. This not only provides a smoother frequency spec-
trum but also ensures that the switching regulator remains
stable by preventing abrupt changes in frequency.
When the PLL mode is enabled, if the external clock fre-
quency is greater than the internal oscillator’s frequency
(OSC), then current is sourced continuously, pulling up the
voltage on the CAP pin. If the external clock frequency is
less than OSC, current is sunk continuously, pulling down
the voltage on the CAP pin. When the external and internal
frequencies are the same but exhibit a phase difference,
current pulses (sourcing or sinking) are used for an amount
Δ V OUT L I ? ESR +
?
?
1 ?
8 fC OUT ? ?
(3)
of time corresponding to the phase difference. The current
pulses adjust the voltage on the CAP pin until the phase
and frequency of the internal and external oscillators are
where f = operating frequency, C OUT = output capacitance
and Δ I L = ripple current in the inductor. For a ?xed output
voltage, the output ripple is highest at maximum input
voltage since Δ I L increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount con?gurations. In the case of
tantalum, it is critical that the capacitors are surge tested
identical. At the stable operating point, the CAP pin is high
impedance and the external capacitor holds the voltage.
The external cap is used by the PLL’s loop ?lter to help
smooth out the voltage change and provide a stable input
to the voltage-controlled oscillator. The value of C1 will
determine how fast the loop acquires lock. Typically C1
is 1nF to 10nF in PLL mode. A value of 2.2nF is suitable
in most applications.
3543fa
12
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