参数资料
型号: LTC3543EDCB#TRPBF
厂商: Linear Technology
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3543
APPLICATIONS INFORMATION
Using Ceramic Capacitors for C IN , C OUT and C1
0.6V
V OUT < 5.5V
High value, low cost ceramic capacitors are now becoming
available in smaller case sizes. Their high ripple current,
V FB
R2
high voltage rating and low ESR make them ideal for switch-
ing regulator applications. Because the LTC3543’s control
LTC3543
R1
loop does not depend on the output capacitor’s ESR for
stable operation, ceramic capacitors can be used freely to
achieve very low output ripple and small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V IN . This ringing can couple to
the output and be mistaken as loop instability. Even worse,
the sudden inrush of current through the long wires can
potentially cause a voltage spike at V IN , large enough to
damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by a resistor divider according
GND
3543 F03
Figure 3. Setting Output Voltage
Ef?ciency Considerations
The ef?ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the ef?ciency and which change would produce
the most improvement. Ef?ciency can be expressed as:
Ef?ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3543 circuits: V IN quiescent current and
I 2 R losses. The V IN quiescent current loss dominates
V OUT = 0 . 6 V ? ? 1 +
to the following formula:
? R2 ?
?
? R 1 ?
(4)
the ef?ciency loss at very low load currents whereas the
I 2 R loss dominates the ef?ciency loss at medium to high
load currents. In a typical ef?ciency plot, the ef?ciency
curve at very low load currents can be misleading since
The external resistor divider is connected to the output
allowing remote voltage sensing as shown in Figure 3.
the actual power lost is of no consequence as illustrated
in Figure 4.
500
400
300
200
100
0
V OUT = 1.2V
V OUT = 1.5V
V OUT = 1.8V
V OUT = 2.5V
0.1
1
10 100
LOAD CURRENT (mA)
1000
3543 F04
Figure 4. Power Loss vs Load Current
3543fa
13
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LTC3544BEUD#PBF 功能描述:IC REG BUCK SYNC ADJ QUAD 16QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压(降压) 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON(1.45x1) 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2
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