参数资料
型号: LTC3568EDD#PBF
厂商: Linear Technology
文件页数: 12/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.8A 10DFN
标准包装: 121
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 最高 4MHz
电流 - 输出: 1.8A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
产品目录页面: 1335 (CN2011-ZH PDF)
LTC3568
APPLICATIONS INFORMATION
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V OUT im-
mediately shifts by an amount equal to Δ I LOAD ? ESR, where
ESR is the effective series resistance of C OUT . Δ I LOAD also
begins to charge or discharge C OUT generating a feedback
error signal used by the regulator to return V OUT to its
steady-state value. During this recovery time, V OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
C F can be added to improve the high frequency response,
as shown in Figure 5. Capacitor C F provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V IN drops toward V OUT , the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
In some applications, a more severe transient can be caused
by switching in loads with large (>1uF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C OUT , causing a rapid drop in V OUT . No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
V IN
2.5V
TO 5.5V
C6
+
C IN
R6
R5
C F
PGND
PGND
C8
SGND
SV IN PV IN
LTC3568
SYNC/MODE
PGOOD
SW
PGOOD
L1
+
C OUT
C5
V OUT
SGND
C ITH
R C
C C
I TH
SGND PGND
V FB
SHDN/R T
R T
R1
R2
PGND
PGND
SGND
SGND
GND
SGND SGND
3568 F05
Figure 5. LTC3568 General Schematic
3568fa
  
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