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参数资料
| 型号： | LTC3589IUJ-1#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封装： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 27/46页 |
| 文件大小： | 570K |
| 代理商： | LTC3589IUJ-1#TRPBF |
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LTC3589/LTC3589-1
33
3589fc
OPERATION
Figure 17. IRQ and IRQSTAT Status Register Fault Timing
IRQ
IRQSTAT
CLIRQ
3589 F17
TSD, UV,
OR PGOOD FAULT
1 SEC
Figure 16. IRQ and IRQSTAT Status Register Warning Timing
IRQ
IRQSTAT
CLIRQ
3589 F16
TSD OR UV
WARNING
Thermal Shutdown Fault and Warning
Similar to the VIN undervoltage detection circuits the over-
temperature detection circuits check for warning and fault
levels. An overtemperature fault will initiate a fault induced
shutdown. An overtemperature warning sets register bit
IRQSTAT[6] and pulls the IRQ pin LOW.
IRQ Pin and IRQSTAT Status Register Function
The IRQ pin and IRQSTAT status register report PGOOD
timeout fault, VIN undervoltage warning and fault, and
high temperature warning and fault. Table 16 shows the
meaning of the IRQSTAT read-only status register bits.
Table 16. IRQSTAT Read-Only Register Bit Definitions
IRQSTAT[BIT]
VALUE
SETTING
31
PGOOD Timeout Fault (PGOOD Low >
14ms)
41
VIN Undervoltage Warning (VIN < 2.9V)
51
VIN Undervoltage Fault (VIN < 2.6V)
61
Thermal Limit Warning (TJ > 130°C)
71
Thermal Limit Fault (TJ > 150°C)
Figure 16 shows the timing of the IRQ and IRQSTAT status
register following a warning (VIN<2.9Vorhightemperature
warning) event. When a warning occurs, IRQ is latched
LOW and bit IRQSTAT[4] or IRQSTAT[5] is set. IRQ remains
low and the IRQSTAT status bits remain active until the
I2C CLIRQ command is given and the warning condition
has passed.
Figure 17 shows the timing of the IRQ pin and IRQSTAT
status register following a fault induced hard shutdown
event. When a fault occurs, IRQ is latched LOW and bit
IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-
mains LOW until the CLIRQ command is issued. When the
CLIRQ command has been issued, the IRQSTAT status bit
remains set for the one second enable inhibit time or as
long as the fault condition persists, whichever is longer.
Fault Induced Shutdown
Any of the three fault conditions will initiate a hard reset
shutdown triggering the following events: 1) A bit corre-
sponding to the fault is set in status register IRQSTAT, 2)
IRQ and WAKE pins are pulled LOW, 3) enable pin inputs
are ignored and the regulators are disabled, 4) all enable
bits and software control mode bit in the output voltage
enable OVEN command register are cleared, and 5) the
pushbutton controller is sent to the PDN state for one
second and then to POFF. Re-enabling of regulators is
inhibited until both the fault condition and the one second
time out have passed to allow regulator outputs sufficient
time to discharge. When one second timeout and the fault
condition are both passed, if PWR_ON is HIGH, WAKE will
come up and the LTC3589 will respond to any enable pins
that are also HIGH.
I2C OPERATION
I2C Interface
The LTC3589/LTC3589-1 communicates with a bus master
using the standard I2C 2-wire interface. The two bus lines,
SDA and SCL, must be HIGH when the bus is not in use.
External pull-up resistors or current sources, such as the
LTC1694 SMBus accelerator, are required on these lines.
The LTC3589 is both a slave receiver and slave transmitter.
The I2C control signals, SDA and SCL are scaled internally
to the DVDD supply. DVDD should be connected to the same
power supply as the bus pull-up resistors.
The I2C port has an undervoltage lockout on the DVDD
pin. When DVDD is below approximately 1V, the I2C serial
port is reset to power-on states and registers are set to
default values.
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