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参数资料
| 型号： | LTC3589IUJ#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封装： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 25/46页 |
| 文件大小： | 570K |
| 代理商： | LTC3589IUJ#PBF |
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LTC3589/LTC3589-1
31
3589fc
V1
V3
V2
V4
LDO2
LDO3
LDO4
3589 F12
WAKE
1.8V
2.8V
1.2V
3.3V
0.5V
1.8V
1V
1.2V
200μs
Figure 12. Pin-Strap Sequencing Timing
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
LDO1
RSTO
VIN 2.7V
–8%
1 SEC
INITIAL POWER-UP
LTC3589
LDO1 UNDERVOLTAGE
25μs
14ms
3589 F13
LDO1
RSTO
VIN
–8%
INITIAL POWER-UP
LTC3589-1
LDO1 UNDERVOLTAGE
25μs
14ms
Keep-Alive Operation
For systems which require an active supply rail when in
system standby, any of the three LTC3589/LTC3589-1
step-down switching regulators or LDO2 may be kept
alive regardless of the status of PWR_ON and WAKE.
Writing a 1 to a regulator’s keep-alive bit in its dynamic
target voltage register will keep a regulator alive when the
LTC3589/LTC3589-1 is in standby mode. A regulator with
its keep-alive bit set will stay enabled until the bit is reset
writing the bit LOW, resetting the LTC3589/LTC3589-1
with a pushbutton hard reset, or a fault condition (UVLO,
PGOOD, timeout or thermal shutdown) occurs. PGOOD
and fault status are reported in the IRQSTAT and PGSTAT
registers and on the IRQ and PGOOD pins for keep-alive
regulators when PWR_ON and WAKE are LOW.
Software Control Mode
Once a power-up sequence is completed each regulator
may be enabled and disabled individually by the system
as needed for power mode requirements. Setting the out-
put voltage enable command register bit OVEN[7] HIGH
disconnects each regulator from its enable pin so control
is solely through the OVEN command register. To enter
software control mode, set command bit OVEN[7] HIGH
and the desired enable bits in OVEN[6:0] HIGH. Any of the
regulators enabled in OVEN[6:0] will stay on regardless of
the state of their enable pins when OVEN[7] is HIGH. Set-
ting the regulator enable bits and the software control bit in
OVEN[7] may occur on the same I2C start-stop sequence. A
normal shutdown using PWR_ON resets all eight bits of the
OVEN register to 0x00 to ensure all regulators are shut off.
OPERATION
FAULT DETECTION, SHUTDOWN, AND REPORTING
The LTC3589/LTC3589-1 monitors VIN, output rail voltages
andinternaldietemperature.Awarningconditionisindicated
when VIN is less than 2.9V and when internal die tempera-
ture approaches the thermal shutdown temperature. A fault
condition occurs when VIN is less than 2.6V, any regulator
output is 8% low for 14ms, or the internal die temperature
is HIGH. Warning and fault states are reported via the IRQ,
PGOOD, and RTSO pins. Specific fault states are read via
the I2C serial port status registers IRQSTAT and PGSTAT.
RSTO Pin Function
The RSTO (reset output) pin is an open-drain output for use
as a power-on reset signal. It is pulled LOW at initial power
until LDO1 is within 8% of its target and the initial one second
start-uptimerisfinished.RSTOremainsHIGHduringnormal
operation and will be pulled low if LDO1 loses regulation for
more than 25μs or a pushbutton hard reset is initiated. RSTO
is released high 14ms after LDO1 returns to regulation.
Figure 13 shows a initial power-up for the RSTO pin. If VIN
is not above its undervoltage thresholds at the end of the 1
second start-up time, the IRQ pin will be pulled LOW and an
undervoltage bit will be set in the IRQSTAT status register.
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相关代理商/技术参数 |
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