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| 型号： | LTC3603IUF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 20QFN |
| 标准包装： | 91 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14.5 V |
| 输入电压： | 4.5 V ~ 15 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 300kHz ~ 3MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
LTC3603
APPLICATIONS INFORMATION
V BURST =
I BURST
+ 0.42V
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is in the range of
0.42V to 1V, Burst Mode operation is enabled. During
Burst Mode operation, the voltage on the SYNC/MODE
pin determines the burst clamp level. This level sets the
minimum peak inductor current, I BURST , for each switching
cycle according to the following equation:
6A/V
V BURST is the voltage on the SYNC/MODE pin. I BURST
can be programmed in the range of 0A to 3.5A, which
corresponds to a V BURST range of 0.42V to 1V. As the output
load current drops, the peak inductor current decreases
to keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I BURST , the burst clamp will force the peak inductor
current to remain equal to I BURST regardless of further
reductions in the load current. Since the average inductor
current is therefore greater than the output load current,
the voltage on the ITH pin will decrease. When the I TH
voltage drops to 330mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
again when the output voltage drops out of regulation. The
value for I BURST is determined by the desired amount of
output voltage ripple. As the value of I BURST increases, the
sleep time between pulses and the output voltage ripple
increases. The burst clamp voltage, V BURST , can be set
by a resistor divider from the INTV CC pin. Alternatively,
the SYNC/MODE pin may be tied directly to the V FB pin to
set V BURST = 0.6V (I BURST = 1A), or through an additional
divider resistor (R3) to set V BURST = 0.42V to 0.6V (see
Figure 2).
R2
INTV CC FB V OUT
LTC3603 R2 LTC3603 R3 (OPTIONAL)
Pulse skipping, which is a compromise between low output
voltage ripple and efficiency, can be implemented by con-
necting the SYNC/MODE pin to ground. This sets I BURST to
0A. In this condition, the peak inductor current is limited by
the minimum on-time of the current comparator and the
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3603’s internal oscillator can be synchronized to
an external 5V clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 3MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the R T resistor. Because slope compensation is generated
by the oscillator’s internal ramp, the external frequency
should be set 25% higher than the frequency set by the
R T resistor to ensure that adequate slope compensation
is present. When synchronized, the LTC3603 will operate
in pulse-skipping mode. Do not allow the SYNC/MODE
pin to float when the external clock signal is not active.
In some cases, a pull-down resistor on SYNC/MODE may
be needed to avoid this.
INTV CC Regulator
The LTC3603 features an integrated P-channel low dropout
linear regulator (LDO) that supplies power to the INTV CC
supply pin from the PV IN pin. This LDO supply has been
designed to deliver up to 35mA of load current for the
powering of the internal gate drivers and other internal
circuitry. A small external load may also be applied provided
that the total current from the INTV CC supply does not
exceed 35mA. The INTV CC pin should be bypassed with
no less than a 0.22μF ceramic capacitor. A 1μF ceramic
capacitor is suitable for most applications.
SYNC/MODE
SYNC/MODE
R1
R1
Topside MOSFET Driver Supply (BOOST Pin)
SGND SGND
3603 F02
V BURST = 0.42V TO 1V V BURST = 0.42V TO 0.6V
Figure 2. Programing the Burst Clamp
The LTC3603 uses a bootstrapped supply to power the
gate of the internal topside MOSFET (Figure 3). When the
topside MOSFET is off and the SW pin is low, diode D BST
charges capacitor C BST to the voltage on the INTV CC supply.
12
For more information www.linear.com/LTC3603
3603fc
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