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参数资料
| 型号： | LTC3606BIDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.8A 8DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN-EP（3x3） |
LTC3606B
OPERATION
Figure 1a shows V IN (I IN ) current below input current
limit with a C LIM capacitor of 0.1μF. When the load pulse
is applied, under the speci?ed condition, I LIM current is
1.1A/55k ? 0.66 = 13.2μA, where 0.66 is the duty cycle.
It will take a little more than 7.5ms to charge the C LIM
capacitor from 0V to 1V, after which the LTC3606B begins
to limit input current. The I IN current is not limited during
this 7.5ms time and is more than 725mA. This current
transient may cause the input supply to temporarily
droop if the supply current compliance is exceeded, but
recovers after the input current limit engages. The output
will continue to deliver the required current load while the
output voltage droops to allow the input voltage to remain
regulated during input current limit.
For applications with short load pulse duration, a smaller
C LIM capacitor may be the better choice as in the example
shown in Figure 1b. In this example, a 577μs, 0A to 2A
output pulse is applied once every 4.7ms. A C LIM capacitor
of 2.2nF requires 92μs for V RLIM to charge from 0V to 1V.
During this 92μs, the input current limit is not yet engaged
V OUT
2V/DIV
I IN
500mA/DIV
V RLIM
1V/DIV
I L
1A/DIV
and the output must deliver the required current load.
This may cause the input voltage to droop if the current
compliance is exceeded. Depending on how long this time
is, the V IN supply decoupling capacitor can provide some
of this current before V IN droops too much. In applications
with a bigger V IN supply decoupling capacitor and where
V IN supply is allow to droop closer to dropout, the C LIM
capacitor can be increased slightly. This will delay the
start of input current limit and arti?cially regulated V OUT
before input current limit is engaged. In this case, within
the 577μs load pulse, the V OUT voltage will stay arti?cially
regulated for 92μs out of the total 577μs before the input
current limit activates. This approach may be used if a
faster recovery on the output is desired.
Selecting a very small C LIM will speed up response time
but it can put the device within threshold of interfering
with normal operation and input current limit in every
few switching cycles. This may be undesirable in terms
of noise. Use 2πRC >> 100/clock frequency (2.25MHz) as
a starting point, R being R LIM , C being C LIM .
V OUT
200mV/DIV
V IN
AC-COUPLED
1V/DIV
I OUT
500mA/DIV
I IN
500mA/DIV
50ms/DIV
3606B F01a
1ms/DIV
3606B F01b
V IN = 5V, 500mA COMPLIANT
R LIM = 116k, C LIM = 0.1μF
I LOAD = 0A to 1.1A, C OUT = 2.2mF, V OUT = 3.3V
I LIM = 475mA
Figure 1a. Input Current Limit Within 100ms Load Pulses
V IN = 5V, 500mA COMPLIANT
R LIM = 116k, C LIM = 2200pF
I LOAD = 0A to 2A, C OUT = 2.2mF, V OUT = 3.3V
I LIM = 475mA
Figure 1b. Input Current Limit Within
577μs, 2A Repeating Load Pulses
3606bfb
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