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参数资料
| 型号： | LTC3612IUDC#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/30页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 20QFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.25 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 300kHz ~ 4MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（3x4） |
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LTC3612
APPLICATIONS INFORMATION
Burst Clamp Programming
If the voltage on the MODE pin is less than 0.8V, Burst
Mode operation is enabled.
If the voltage on the MODE pin is less than 0.3V, the in-
ternal default burst clamp level is selected. The minimum
voltage on the ITH pin is typically 525mV (internal clamp).
If the voltage is between 0.45V and 0.8V, the voltage on
the MODE pin (V BURST ) is equal to the minimum voltage
on the ITH pin (external clamp) and determines the burst
clamp level I BURST (typically from 0A to 3.5A).
When the ITH voltage falls below the internal (or external)
clamp voltage, the sleep state is enabled.
As the output load current drops, the peak inductor current
decreases to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than I BURST , the burst clamp will force the peak
inductor current to remain equal to I BURST regardless of
further reductions in the load current.
Since the average inductor current is greater than the out-
put load current, the voltage on the ITH pin will decrease.
When the ITH voltage drops, sleep mode is enabled in
which both power switches are shut off along with most
of the circuitry to minimize power consumption. All cir-
cuitry is turned back on and the power switches resume
operation when the output voltage drops out of regulation.
The value for I BURST is determined by the desired amount
of output voltage ripple. As the value of I BURST increases,
the sleep period between pulses and the output voltage
ripple increase. Note that for very high V BURST voltage
settings, the power good comparator may trip, since the
output ripple may get bigger than the power good window.
Pulse-skipping mode, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting MODE to SV IN . This sets I BURST to 0A. In
this condition, the peak inductor current is limited by the
minimum on-time of the current comparator. The lowest
output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, V OUT shifts by an amount equal
to ? I LOAD(ESR) , where ESR is the effective series resistance
of C OUT . ? I LOAD also begins to charge or discharge C OUT ,
generating the feedback error signal that forces the regula-
tor to adapt to the current change and return V OUT to its
steady-state value. During this recovery time V OUT can
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. The availability of the
ITH pin allows the transient response to be optimized over
a wide range of output capacitance.
The ITH external components (R C and C C ) shown in Fig-
ure 1 provide adequate compensation as a starting point
for most applications. The values can be modified slightly
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. The gain of the loop will be in-
creased by increasing R C and the bandwidth of the loop
will be increased by decreasing C C . If R C is increased by
the same factor that C C is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system. The external capaci-
tor, C C1 , (Figure 1) is not needed for loop stability, but it
helps filter out any high frequency noise that may couple
onto that node. The general purpose buck regulator ap-
plication in the Typical Applications section uses a faster
compensation to improve load step response.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C OUT , causing a rapid drop in V OUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
3612fb
18
For more information www.linear.com/LTC3612
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