参数资料
型号: LTC3614EUDD#PBF
厂商: Linear Technology
文件页数: 23/30页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 24QFN
标准包装: 73
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 300kHz ~ 4MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 24-QFN 裸露焊盘(3x5)
LTC3614
APPLICATIONS INFORMATION
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V IN quiescent current and I 2 R losses. The V IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I 2 R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is the current
out of V IN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V IN ; thus, their effects
will be more pronounced at higher supply voltages.
2. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and external inductor, R L . In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I 2 R losses, simply add R SW to
R L and multiply the result by the square of the average
output current.
Other losses including C IN and C OUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
23
For more information www.linear.com/LTC3614
3614fb
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