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参数资料
| 型号： | LTC3619BIMSE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ DL 10MSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 400mA，800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3619B
OPERATION
Figure 1a shows V IN (I IN ) current below input current limit
with a C LIM capacitor of 0.1μF. Channel 1 is unloaded to
simplify calculations. When the load pulse is applied,
under the specified condition, I LIM current is 1.1A/55k ?
0.66 = 13.2μA, where 0.66 is the duty cycle. It will take a
little more than 7.5ms to charge the C LIM capacitor from
0V to 1V, after which the LTC3619B begins to limit input
current. The I IN current is not limited during this 7.5ms
time and is more than 725mA. This current transient may
cause the input supply to temporarily droop if the supply
current compliance is exceeded, but recovers after the
input current limit engages. The output will continue to
deliver the required current load while the output voltage
droops to allow the input voltage to remain regulated
during input current limit.
For applications with short load pulse duration, a smaller
C LIM capacitor may be the better choice as in the example
shown in Figure 1b. Channel 1 is unloaded for simplifi-
cation. In this example, a 577μs, 0A to 2A output pulse
is applied once every 4.7ms. A C LIM capacitor of 2.2nF
requires 92μs for V RLIM to charge from 0V to 1V. During
V OUT
2V/DIV
I IN
500mA/DIV
V RLIM
1V/DIV
I L
1A/DIV
this 92μs, the input current limit is not yet engaged and
the output must deliver the required current load. This
may cause the input voltage to droop if the current com-
pliance is exceeded. Depending on how long this time is,
the V IN supply decoupling capacitor can provide some of
this current before V IN droops too much. In applications
with a bigger V IN supply decoupling capacitor and where
V IN supply is allow to droop closer to dropout, the C LIM
capacitor can be increased slightly. This will delay the
start of input current limit and artificially regulated V OUT
before input current limit is engaged. In this case, within
the 577μs load pulse, the V OUT voltage will stay artificially
regulated for 92μs out of the total 577μs before the input
current limit activates. This approach may be used if a
faster recovery on the output is desired.
Selecting a very small C LIM will speed up response time
but it can put the device within threshold of interfering
with normal operation and input current limit in every
few switching cycles. This may be undesirable in terms
of noise. Use 2πRC >> 100/clock frequency (2.25MHz) as
a starting point, R being R LIM , C being C LIM .
V OUT
200mV/DIV
V IN
AC-COUPLED
1V/DIV
I OUT
500mA/DIV
I IN
500mA/DIV
50ms/DIV
3619B F01a
1ms/DIV
3619B F01b
V IN = 5V, 500mA COMPLIANT
R LIM = 116k, C LIM = 0.1μF
I LOAD = 0A to 1.1A, C OUT = 2.2mF, V OUT = 3.3V
I LIM = 475mA, CHANNEL 1 NOT LOADED
Figure 1a. Input Current Limit Within 100ms Load Pulses
V IN = 5V, 500mA COMPLIANT
R LIM = 116k, C LIM = 2200pF
I LOAD = 0A to 2A, C OUT = 2.2mF, V OUT = 3.3V
I LIM = 475mA, CHANNEL 1 NOT LOADED
Figure 1b. Input Current Limit Within
577μs, 2A Repeating Load Pulses
3619bfb
10
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