参数资料
型号: LTC3634EFE#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 5.5 A DUAL SWITCHING CONTROLLER, 4600 kHz SWITCHING FREQ-MAX, PDSO28
封装: 4.40 MM, LEAD FREE, PLASTIC, TSSOP-28
文件页数: 16/28页
文件大小: 359K
代理商: LTC3634EFE#PBF
LTC3634
23
3634f
be measured as a function of power loss in the package
with corresponding output load current. Although making
this measurement with this method does violate absolute
maximum voltage ratings on the PGOOD pin, the applied
power is so low that there should be no significant risk
of damaging the device.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3634. Check the following in your layout:
1. Do the input capacitors connect to the VIN and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2. The output capacitor, COUT, and inductor L should be
closely connected to minimize loss. The (–) plate of
COUT should be closely connected to both PGND and
the (–) plate of CIN.
3. The resistive divider, (e.g. R1 and R2 in Figure 1) must
be connected between the (+) plate of COUT and a
ground line terminated near SGND. The feedback signal
VFB should be routed away from noisy components
and traces, such as the SW line, and its trace length
should be minimized. In addition, the RT resistor and
loop compensation components should be terminated
to SGND.
4. Keep sensitive components away from the SW pin.
The RT resistor, the compensation components, the
feedback resistors, and the INTVCC bypass capacitor
should all be routed away from the SW trace and the
inductor L.
5. A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
bothconnectingtoacommon,lownoisereferencepoint.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
Thesecopperareasshouldbeconnectedtotheexposed
backside of the package (PGND). Refer to Figures 10
and 11 for board layout examples.
Design Example
Asadesignexample,considerusingtheLTC3634(asshown
in Figure 1) to power DDR2 SDRAM with the following
specifications:VIN(MAX)=13.2V,IOUT(MAX)=±2A,f=1MHz,
VDROOP(VDDQ) < 60mV, VDROOP(VTT) < 30mV. The following
discussion will use equations from the previous sections.
First, the correct RT resistor value for 1MHz switching
frequency must be chosen. Based on previous discus-
sions, RT is calculated to be
RT =
3.2E11
f
= 320k
The closest standard value is 324k.
Next, select values for R1 and R2 to set channel 1 (VDDQ)
to be 1.8V for DDR2 SDRAM. Choosing R1 to be 12.1k,
R2 is calculated to be:
R2
= 12.1k
1.8V
0.6V
1
= 24.2k
The closest standard value is 24.3k. Tying VDDQIN to
VOUT1 sets VOUT2 to be half of VOUT1.
Next, we can pick inductor values for both the VDDQ and
VTT outputs. Choosing inductor current ripple to be 1A
at maximum VIN:
L1
=
1.8V
1MHz 1A
1
1.8V
13.2V
= 1.55H
L2
=
0.9V
1MHz 1A
1
0.9V
13.2V
= 0.838H
Standard values of 1.5μH and 0.82H should be used.
Ceramic caps will be used for COUT and will be selected
based on the charge storage requirement. Assuming a
worst case 4A load step (–2A to 2A):
COUT1
3 4A
1MHz 60mV
= 200F
COUT2
3 4A
1MHz 30mV
= 400F
applicaTions inForMaTion
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