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参数资料
| 型号： | LTC3703EGN-5#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 16-SSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 96% |
| 电源电压： | 4.1 V ~ 15 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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LTC3703-5
APPLICATIO S I FOR ATIO
MainSwitchDutyCycle =
SynchronousSwitchDutyCycle =
appropriatebreakdownspecification.SincemostMOSFETs
in the 30V to 60V range have logic level thresholds
(V GS(MIN) ≥ 4.5V), the LTC3703-5 is designed to be used
with a 4.5V to 15V gate drive supply (DRV CC pin).
For maximum efficiency, on-resistance R DS(ON) and input
capacitance should be minimized. Low R DS(ON) minimizes
conduction losses and low input capacitance minimizes
V OUT
V IN
V IN – V OUT
V IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
P MAIN =
V OUT
V IN
( I MAX ) 2 ( 1 + δ ) R DR ( ON ) +
V IN 2 MAX ( R DR MILLER ) ?
(Figure 8).
V IN
I
2
)( C
P SYNC = IN OUT ( I MAX ) ( 1 + δ ) R DS ( 0 N )
V – V
V GS
MILLER EFFECT
a b
Q IN
C MILLER = (Q B – Q A )/V DS
V
+
V GS
–
+ V DS
–
? ?
? 1 1 ?
? V CC – V TH ( IL ) V TH ( IL ) ?
V IN
? + ? ( f )
2
37035 F08
Figure 8. Gate Charge Characteristic
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V DS drain voltage, but can be
adjusted for different V DS voltages by multiplying by the
ratio of the application V DS to the curve specified V DS
values. A way to estimate the C MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V DS voltage
specified. C MILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C RSS
and C OS are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
where δ is the temperature dependency of R DS(ON) , R DR is
the effective top driver resistance (approximately 2 ? at
V GS = V MILLER ), V IN is the drain potential and the change
in drain potential in the particular application. V TH(IL) is the
data sheet specified typical gate threshold voltage speci-
fied in the power MOSFET data sheet at the specified drain
current. C MILLER is the calculated capacitance using the
gate charge curve from the MOSFET data sheet and the
technique described above.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V IN < 25V, the
high current efficiency generally improves with larger
MOSFETs, while for V IN > 25V, the transition losses
rapidly increase to the point that the use of a higher
R DS(ON) device with lower C MILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R DS(ON) vs temperature curve, and
typically varies from 0.005/ ° C to 0.01/ ° C depending on
the particular MOSFET used.
duty cycles for the top and bottom MOSFETs are given by:
37035fa
14
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| LTC3703HGN#PBF | 功能描述:IC REG CTRLR BST PWM VM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LTC3703HGN#TRPBF | 功能描述:IC REG CTRLR BST PWM VM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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