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参数资料
| 型号： | LTC3704IMS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR INV PWM CM 10-MSOP |
| 标准包装： | 50 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 97% |
| 电源电压： | 2.5 V ~ 36 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 是 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
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LTC3704
OPERATIO
minimum on-time (about 175ns). Below this output
current level, the converter will begin to skip cycles in
order to maintain output regulation. Figures 3 and 4 show
the light load switching waveforms for Burst Mode and
Pulse-Skip Mode operation for the converter in Figure 1.
buffered I TH burst clamp is removed, allowing the I TH pin
to directly control the current comparator from no load to
full load. With no load, the I TH pin is driven below 0.30V,
the power MOSFET is turned off and sleep mode is
invoked. Oscilloscope waveforms illustrating this mode of
operation are shown in Figure 4.
Burst Mode Operation
Burst Mode operation is selected by leaving the MODE/
SYNC pin unconnected or by connecting it to ground. In
normal operation, the range on the I TH pin corresponding
to no load to full load is 0.30V to 1.2V. In Burst Mode
operation, if the error amplifier EA drives the I TH voltage
below 0.525V, the buffered I TH input to the current com-
parator C1 will be clamped at 0.525V (which corresponds
to 25% of maximum load current). The inductor current
peak is then held at approximately 30mV divided by the
power MOSFET R DS(ON) . If the I TH pin drops below 0.30V,
the Burst Mode comparator B1 will turn off the power
MOSFET and scale back the quiescent current of the IC to
250 μ A (sleep mode). In this condition, the load current will
be supplied by the output capacitor until the I TH voltage
rises above the 50mV hysteresis of the burst comparator.
At light loads, short bursts of switching (where the aver-
age inductor current is 25% of its maximum value) fol-
lowed by long periods of sleep will be observed, thereby
greatly improving converter efficiency. Oscilloscope wave-
forms illustrating Burst Mode operation are shown in
Figure 3.
MODE/SYNC = 0V
(Burst Mode OPERATION)
V OUT
50mV/DIV
I L
5A/DIV
MODE/SYNC = INTV CC
(PULSE-SKIP MODE)
V OUT
50mV/DIV
I L
5A/DIV
2 μ s/DIV 3704 F04
Figure 4. LTC3704 Low Output Current Operation with Burst
Mode Operation Disabled (MODE/SYNC = INTV CC )
When an external clock signal drives the MODE/SYNC pin
at a rate faster than the chip’s internal oscillator, the
oscillator will synchronize to it. In this synchronized mode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the
expense of overall system efficiency of light loads.
When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the internal
oscillator ramp is terminated early and the slope compen-
sation is increased by approximately 30%. As a result, in
applications requiring synchronization, it is recommended
that the nominal operating frequency of the IC be pro-
grammed to be about 75% of the external clock frequency.
Attempting to synchronize to too high an external fre-
quency (above 1.3f O ) can result in inadequate slope com-
pensation and possible subharmonic oscillation (or jitter).
10 μ s/DIV
3704 F03
The external clock signal must exceed 2V for at least 25ns,
Figure 3. LTC3704 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
Pulse-Skip Mode Operation
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
With the MODE/SYNC pin tied to a DC voltage above 1.2V,
Burst Mode operation is disabled. The internal, 0.525V
3704fb
9
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