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参数资料
| 型号： | LTC3723EGN-2#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO VM 16SSOP |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 50% |
| 电源电压： | 10V（最小值） |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
LTC3723-1/LTC3723-2
OPERATIO
very low (145 μ A typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
The trickle charge resistor should be selected as follows:
R START(MAX) = V IN(MIN) – 10.7V/250 μ A
Adding a small safety margin and choosing standard
values yields:
UVLO. The amount of DC feed hysteresis provided by this
current is: 10 μ A ? R TOP , (Figure 3). The system UVLO
threshold is: 5V ? {(R TOP + R BOTTOM )/R BOTTOM }. If the
voltage applied to UVLO is present and greater than 5V
prior to the V CC UVLO circuitry activation, then the internal
UVLO logic will prevent output switching until the follow-
ing three conditions are met: (1) V CC UVLO is enabled, (2)
APPLICATION
DC/DC
Off-Line
PFC Preregulator
V IN RANGE
36V to 72V
85V to 270V RMS
390V DC
R START
100k
430k
1.4M
V REF is in regulation and (3) UVLO pin is greater than 5V.
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 3 provides this capability.
V CC should be bypassed with a 0.1 μ F to 1 μ F multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V CC supply before the
R TOP
UVLO
bootstrap winding, or an auxiliary regulator circuit takes
over.
ON OFF
R BOTTOM
C HOLDUP = (I CC + I DRIVE ) ? t DELAY /3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3723-1/LTC3723-2. Refer to
Figure 2 for various bias supply configurations.
372312 F03
Figure 3. System UVLO Setup
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide V CC
voltage to the LTC3723-1/LTC3723-2 and supporting
12V ± 10%
1.5k
1N5226
3V
V IN
V BIAS < V UVLO
1N914
R START
circuitry, one must be generated. Since the power require-
ment is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
V CC
1 μ F
V CC
1 μ F
+
C HOLD
372312 F02
and lowest cost approach. One method that works well is
toaddawindingtothemainpowertransformer,andpost
regulate the resultant square wave with an L-C filter (see
Figure 2. Bias Configurations
Programming Undervoltage Lockout
The LTC3723-1/LTC3723-2 provides undervoltage lock-
out (UVLO) control for the input DC voltage feed to the
Figure 4a). The advantage of this approach is that it
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include
a primary winding for this purpose in their standard
power converter in addition to the V CC UVLO function
described in the preceding section. Input DC feed UVLO is
provided with the UVLO pin. A comparator on UVLO
V IN
R START
V CC
compares a divided down input DC feed voltage to the 5V
precision reference. When the 5V level is exceeded on
15V*
+
C HOLD
2k
1 μ F
UVLO, the SS pin is released and output switching com-
mences. At the same time a 10 μ A current is enabled which
*OPTIONAL
372312 F04a
flows out of UVLO into the voltage divider connected to
Figure 4a. Auxiliary Winding Bias Supply
372312f
11
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