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参数资料
| 型号： | LTC3773EUHF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PQCC38 |
| 封装： | 5 X 7 MM, PLASTIC, MO-220WHKD, QFN-38 |
| 文件页数： | 16/32页 |
| 文件大小： | 461K |
| 代理商： | LTC3773EUHF |
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LTC3773
23
3773fa
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the PLLFLTR pin. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the oscillators
are identical. At the stable operating point, the phase
detector has high impedance and the lter capacitor CLP
holds the voltage.
The loop lter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The lter
components CLP and RLP determine how fast the loop ac-
quires lock. Typically RLP = 10k and CLP is 0.01F to 0.1F.
The external clock (on the PLLIN/FC pin) input threshold
is typically 1V. Table 2 summarizes the different states in
which the PLLIN/FC and PLLFLTR pins can be used.
Table 2. PLLFLTR Pin Voltage vs Switching Frequency
PLLFLTR
PLLIN/FC
FREQUENCY
GND
DC Voltage
220kHz
Floating
DC Voltage
400kHz
VCC
DC Voltage
560kHz
RC Loop Filter
Clock Signal
Phase-Locked
to External Clock
Figure 6b. Relationship Between Oscillator Frequency
and Voltage at the PLLFLTR Pin When Synchronizing
to an External Clock
VPLLFLTR (V)
0
0.5
1
1.5
2
2.5
3.0
SYNCHRONIZATION
SWITCHING
FREQUENCY
(kHz)
800
3773 F06b
700
400
500
600
300
200
100
VCC = 5V
Figure 6a. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
VCC
RLP
CLP
3773 F06a
PLLFLTR
EXTERNAL
OSCILLATOR
PLLIN/
FC
APPLICATIONS INFORMATION
turn-on of controller 2’s/3’s external N-channel MOSFET
and CLKOUT signal are controlled by the PHASEMD
pin as showed in Table 1. Note that when PHASEMD is
forced high, controller 2 and controller 3 outputs can be
connected in parallel to produce a higher output power
voltage source.
Table 1. Phase Relationship between the PLLIN/FC Pin vs
Controller 1, 2, 3 Top Gate and CLKOUT Pin
PHASEMD
CH1
CH2
CH3
CLKOUT
GND
0 Deg
120 Deg
240 Deg
60 Deg
Floating
0 Deg
120 Deg
240 Deg
0 Deg
VCC
0 Deg
90 Deg
270 Deg
180 Deg
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
A simplied Phase-Locked Loop Block Diagram is shown
in Figure 6a. The output of the phase detector is a pair of
complementary current sources that charge or discharge
the external lter network connected to the PLLFLTR pin.
The relationship between the voltage on the PLLFLTR pin
and operating frequency, when there is a clock signal ap-
plied to PLLIN/FC, is shown in Figure 6b and specied in
the Electrical Characteristics table. Note that the LTC3773
can only be synchronized to an external clock whose
frequency is within range of the LTC3773’s internal VCO,
which is nominally 160kHz to 700Hz. This is guaranteed,
over temperature and variations, to be between 200kHz
and 540kHz.
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