参数资料
型号: LTC3785EUF#PBF
厂商: Linear Technology
文件页数: 16/20页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 24-QFN
标准包装: 91
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1MHz
占空比: 99%
电源电压: 2.7 V ~ 10 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3785
APPLICATIONS INFORMATION
I L(MAX _ AV) =
? 3 2 ? 1.3 ? 0.025 = 0.20W
PB(BUCK) =
? 3 2 ? 1.3 ? 0.025 = 0.10W
PD(BOOST) =
I L(MAX _ AV) =
= 4.6A
V OUT ?I OUT ? %Loss
ESR L(MAX) ~ = 24m Ω
I L(MAX _ AV) ? 100
? 3.3
?
PA(BOOST) = ? ? 3 ? ? 1.3 ? 0.025 = 0.43W
+ 1? 3.3 3 ?
? 0.45 – 9 ? 500 ? 10 3
R ILSET =
Ω
R ILSET =
= 42k
DeterminetheProperInductorTypeSelection
The highest inductor current is during boost mode and
is given by:
V OUT ?I OUT
V IN ? η
where η = estimated efficiency in this mode (use 80%).
3.3 ? 3
2.7 ? 0.8
To limit the maximum efficiency loss of the inductor ESR
to below 5% the equation is:
2
A suitable inductor for this application could be a Coiltron-
ics CD1-3R8 which has a rating DC current of 6A and ESR
of 13m?.
Choose a Proper MOSFET Switch
Using the same guidelines for ESR of the inductor, one
suitable MOSFET could be the Siliconix Si7940DP which
is a dual MOSFET in a surface mount package with 25m Ω
at 2.5V and a total gate charge of 12nC.
Checking the power dissipation of each switch will ensure
reliable operation since the thermal resistance of the
package is 60°C/W.
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
of T J = 100°C with ρ 100C = 1.3, the power dissipation at
V IN = 2.7, and using the equations from the Efficiency
Considerations section:
2
? 2.7 ?
PC(BOOST) = ( 3.3 – 2.7 ) ? 3.3 ? 3 2 ? 1.3 ? 0.025
2.7
3
2.7
= 0.09W
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
10 – 3.3
10
3.3
10
Now to double check the T J of the package with 50°C
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst-case. For applications
where the MOSFETs are in separate packages each device’s
maximum T J would have to be calculated.
T J(PKG1) = T A + θ JA (PA + PB)
= 50 + 60 ? (0.43 + 0.20) = 88°C
T J(PKG2) = T A + θ JA (PC + PD)
= 50 + 60 ? (0.09 + 0.10) = 60°C
Set The Maximum Current Limit
The equation for setting the maximum current limit of the
IC is given by:
6000
R DS(ON)A ?I LIMIT
The maximum current is set 25% above I L(PEAK) to account
for worst-case variation at 100°C = 6A.
6000
0.025 ? 6
Choose the Input and Output Capacitance
The input capacitance should filter current ripple which is
worst-case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10m Ω or less will yield an
input ripple of 60mV.
The output capacitance should filter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
3785fc
  
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