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参数资料
| 型号： | LTC3806EDE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBACK PWM 12-DFN |
| 标准包装： | 91 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 290kHz |
| 占空比： | 94% |
| 电源电压： | 10 V ~ 75 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 包装： | 管件 |
LTC3806
APPLICATIO S I FOR ATIO
V GS
MILLER EFFECT
V IN ? V DS
Compare T J against your initial estimate for T J and if
necessary, recompute δ , power dissipations and T J . Iter-
ate as necessary.
a b
Q IN
C MILLER = (Q B – Q A )/V DS
+
V GS
–
I GATE
3806 F06
DEVICE
UNDER TEST
Selecting the Compensation Network
Load step testing can be used to empirically determine
compensation. Application Note 25 provides information
Figure 6. Gate Charge Curve and Test Circuit
charge (the increase in coulombs on the horizontal axis
from a to b while the curve is flat) is specified for a given
V DS , but can be adjusted for different V DS voltages by
multiplying by the ratio of the application V DS to the curve
specified V DS values. To estimate the C MILLER term, take
the change in gate charge from points a and b on the
manufacturers data sheet and divide by the specified V DS .
With C MILLER determined, calculate the primary-side power
MOSFET power dissipation:
on the technique. When the regulator has multiple out-
puts, compensation should be optimized for the master
output.
PC Board Layout Checklist
1. In order to minimize switching noise and improve out-
put load regulation, the GND pin of the LTC3806 should
be connected directly to 1) the negative terminal of the
INTV CC decoupling capacitor, 2) the negative terminal
of the output decoupling capacitors, 3) the bottom ter-
minal of the current sense resistor, 4) the negative ter-
minal of the input capacitor and 5) at least one via to the
P DPRI RMSPRI DS ( ON ) ( 1 + δ ) + V IN ( MAX )
= I
? R
? R DR MILLER ? ?
? V INTVCC – V TH ? ?
D MIN
2
? ? C
P IN ( MA X ) ? 1 ?
? f
ground plane immediately adjacent to Pin 7 (GND).
2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
where R DR is the GATE1 driver resistance (maximum is
approximately 6 Ω ), V TH is the typical gate threshold volt-
age for the specified power MOSFET and f is the operating
frequency, typically 250kHz. The term (1 + δ ) is generally
given for a MOSFET in the form of a normalized R DS(ON) vs
temperature curve, but δ = 0.005/ ° C can be used as an
approximation for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate at
substantially lower V DS , so transition losses can be ne-
glected. The dissipation may be calculated using:
P DSEC = I RMSSEC2 ? R DS(ON) (1 + δ )
For a known power dissipation in the power MOSFETs, the
junction temperatures can be obtained from the equation:
T J = T A + P D ? R TH(JA)
where T A is the ambient temperature and R TH(JA) is the
MOSFET thermal resistance from junction to ambient.
high output current power supplies. If the ground plane
is to be used for high DC currents, choose a path away
from the small-signal components.
3. Place the C VCC capacitor immediately adjacent to the
INTV CC and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate drive currents. A low
ESR X5R 4.7 μ F ceramic capacitor works well here.
4. The high di/dt loop from the bottom terminal of the
input capacitor through the sense resistor, primary-
side power MOSFET, transformer primary and back
through the input capacitor should be kept as tight as
possible in order to reduce EMI. Also keep the loops
formed by the outputs as tight as possible.
5. Check the switching waveforms of the MOSFETs using
the actual PC board layout. Measure directly across the
power MOSFET terminals to verify that the BV DSS
specification of the MOSFET is not exceeded due to
inductive ringing. If this ringing cannot be avoided and
3806fb
16
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