参数资料
| 型号： | LTC3819EG#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR STEP DOWN 36-SSOP |
| 标准包装： | 2,000 |
| 应用： | 控制器，Sun 服务器 |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 1.03 V ~ 1.41 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 带卷 (TR) |
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LTC3819
PI FU CTIO S
RUN/SS (Pin 1): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
ground at this pin sets the ramp time to full current output.
Forcing this pin below 0.8V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.
SENSE1 + , SENSE2 + (Pins 2,14): The (+) Input to Each
Differential Current Comparator. The I TH pin voltage and
built-in offsets between SENSE – and SENSE + pins in
conjunction with R SENSE set the current trip threshold.
SENSE1 – , SENSE2 – (Pins 3,13): The (–) Input to the
Differential Current Comparators.
EAIN (Pin 4): Input to the error amplifier that compares the
feedback voltage to the internal 0.6V reference voltage.
This pin is normally connected to a resistive divider from
the output of the differential amplifier (DIFFOUT).
PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator. Do not apply voltage to this pin prior to
application of V IN .
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50k ? . The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both output stages. Pulling this pin below 0.6V
will force continuous synchronous operation. Do not
I TH (Pin 8): Error Amplifier Output and Switching Regula-
tor Compensation Point. Both current comparator’s thresh-
olds increase with this control voltage. The normal voltage
range of this pin is from 0V to 2.4V
SGND (Pin 9): Signal Ground. This pin is common to both
controllers. Route separately to the PGND pin.
V DIFFOUT (Pin 10): Output of a Differential Amplifier. This
pinprovidestrueremoteoutputvoltagesensing.V DIFFOUT
normally drives an external resistive divider that sets the
output voltage.
V OS– , V OS+ (Pins 11, 12): Inputs to an Operational Ampli-
fier. Internal precision resistors configure it as a differen-
tial amplifier whose output is V DIFFOUT .
ATTENOUT (Pin 15): Voltage Feedback Signal Resistively
Divided According to the VID Programming Code.
NO_CPU (Pin 16): Open-Drain Logic Output. NO_CPU is
pulled to ground if VID0 to VID3 are all high.
VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic
Input Pins.
V BIAS (Pin 22): Supply Pin for the VID Control Circuit.
ATTENIN (Pin 23): The Input to the VID Controlled Resis-
tive Divider.
TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top
N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTV CC superim-
posed on the switch node voltage SW.
leave this pin floating without a decoupling capacitor.
3819f
8
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