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参数资料
| 型号： | LTC3824IMSE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 10-MSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 600kHz |
| 占空比： | 100% |
| 电源电压： | 4 V ~ 60 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
LTC3824
APPLICATIONS INFORMATION
(I OUT ) 2 (1 + δ )R DS(ON)
V OUT + V D
V IN + V D
L =
= 12 μ H
R SENSE =
= 0.03 Ω
2.PowerMOSFETswitchingandcondutionlosses:
P MOSFET =
+ K(V IN ) 2 (I OUT )(C RSS )(f)
3. The I 2 R losses of the current sense resistor:
P (SENSE R) = (I OUT ) 2 ? R ? D
where D is the duty cycle
4. The inductor loss due to winding resistance:
P (WINDING) = (I OUT ) 2 ? R W
5. Loss of the catch diode:
P (DIODE) = I OUT ? V D ? (1–D)
6. Other losses, including C IN and C OUT ESR dissipation
and inductor core losses, generally account for less
than 2% of total losses.
PCB Layout Considerations
To achieve best performance from a LTC3824 circuit, the PC
board layout must be carefully designed. For lower power
applications, a 2-layer PC board is sufficient. However, at
higher power levels, a multiple layer PC board is recom-
mended. Using a solid ground plane under the circuit is
the easiest way to ensure that switching noise does not
affect the operation.
In order to help dissipate the power from the MOSFET and
diode, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for the MOSFET and diode in order to improve the
spreading of heat from these components into the PCB.
For best electrical performance the LTC3824 circuit should
be laid out as following:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
and output capacitors and current sense resistor in a way
that minimizes the distance between the pads connected
to ground plane.
Place the LTC3824 and associated components tightly
together and next to the section with power components.
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
Connect the current sense input directly to the current
sense resistor pad. V CC and SENSE are the inputs of the
internal current sense amplifier and should be connected
as close to the sense resistor pads as possible. A 100pF
capacitor is required across the V CC and sense pins for
noise filtering and should be placed as close to the pins
as possible.
Design Example
As an example, the LTC3824 is designed for an automo-
tive 5V power supply with the following specifications:
Maximum I OUT = 2A, typical V IN = 6V to 18V and can reach
60V briefly during load dump condition, and operating
switching frequency = 400kHz.
For f = 400kHz, R SET is chosen to be 180k.
Allow inductor ripple current to be 0.8A (40% of the
maximum output current) at V IN = 18V,
(18V – 5V)5V
(400kHz ? 0.8A)18V
C OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design
a 220μF tantalum capacitor is used.
For worse-case conditions C IN should be rated for at least
1A ripple current (half of the maximum output current). A
47μF tantalum capacitor is adequate.
A current limit of 3.3A is selected and R SENSE can be
calculated by :
100mV
3.3A
and a 25mΩ resistor can be used.
3824fg
11
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