参数资料
型号: LTC3829EUHF#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PQCC38
封装: 5 X 7 MM, LEAD FREE, PLASTIC, M0-220WHKD, QFN-38
文件页数: 15/40页
文件大小: 478K
代理商: LTC3829EUHF#PBF
LTC3829
3829f
applicaTions inForMaTion
Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
VIN >> VOUT, the top MOSFETs’ on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturershavedesignedspecialpurposedevicesthat
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BVDSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
RDS(ON), input capacitance, input voltage and maximum
outputcurrent.MOSFETinputcapacitanceisacombination
of several components but can be taken from the typical
gatecharge curveincludedonmostdatasheets(Figure9).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time.
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle
V
Synchronous Switc
OUT
IN
=
hh Duty Cycle
V
IN
OUT
IN
=
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
V
I
N
R
V
MAIN
OUT
IN
MAX
DS ON
IN
=
+
( )
+
( )
2
1
δ
( )
22
2
1
I
R
C
V
MAX
DR
MILLER
CC
TH IL
(
)(
)
+
( )
TTH IL
SYNC
IN
OUT
IN
MAX
f
P
V
I
N
( )
=
+
( )
2
1
δ RDS ON
( )
+
VDS
VIN
3729 F09
VGS
MILLER EFFECT
QIN
a
b
CMILLER = (QB – QA)/VDS
VGS
V
+
Figure 9. Gate Charge Characteristic
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