参数资料
型号: LTC3832-1ES8#TRPBF
厂商: Linear Technology
文件页数: 18/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 360kHz
占空比: 95%
电源电压: 3 V ~ 8 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC3832/LTC3832-1
APPLICATIO S I FOR ATIO
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3832. This helps to minimize internal ground dis-
turbances in the LTC3832 and prevent differences in ground
potential from disrupting internal circuit operation. This
connection should then tie into the ground plane at a single
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFET Q2. Do not tie this single point ground in the trace
run between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.
PV CC
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V CC , PV CC1 and PV CC2 decoupling capacitors should
be as close to the LTC3832 as possible. The 4.7 μ F and 1 μ F
bypass capacitors shown at V CC , PV CC1 and PV CC2 will help
provide optimum regulation performance.
5. The (+) plate of C IN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An additional
1 μ F ceramic capacitor between V IN and power ground is
recommended.
6. The SENSE and V FB pins are very sensitive to pickup from
the switching node. Care should be taken to isolate SENSE
and V FB from possible capacitive coupling to the inductor
switching signal. Connecting the SENSE + and SENSE – close
to the load can significantly improve load regulation.
7. Kelvin sense I MAX and I FB at Q1’s drain and source pins.
V IN
4.7 μ F
+
1 μ F
100 ?
V CC
PV CC2
PV CC1
PGND
1 μ F
0.1 μ F
+
C IN
GND
LTC3832
G1
I MAX
1k
Q1A
Q1B
L O
NC
FREQSET
SHDN
COMP
I FB
SENSE +
G2
Q2
V OUT
C1
SS
FB
NC
+
SENSE –
C OUT
R C
C C
C SS
GND
GND
PGND
PGND
3832 F11
Figure 11. Typical Schematic Showing Layout Considerations
sn3832 3832fs
18
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LTC3832EGN#PBF 功能描述:IC REG CTRLR BUCK PWM VM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR)
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