参数资料
型号: LTC3833EFE#PBF
厂商: Linear Technology
文件页数: 4/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 20TSSOP
标准包装: 74
PWM 型: 电流模式
输出数: 1
频率 - 最大: 2.2MHz
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件
LTC3833
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at T A = 25°C. V IN = 15V, V FB = V OSNS+ – V OSNS– , unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers
R TG(HI)
R TG(LO)
R BG(HI)
R BG(LO)
t DLY(OFF)
t DLY(ON)
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
Top Gate Off to Bottom Gate On
Delay Time
Bottom Gate Off to Top Gate On
Delay Time
TG High
TG Low
BG High
BG Low
(Note 6)
(Note 6)
2.5
1.2
2.5
0.8
20
15
Ω
Ω
Ω
Ω
ns
ns
Internal V CC Regulator and External V CC
INTV CC
INTV CC (%)
EXTV CC(TH)
Internal V CC Voltage
Internal V CC Load Regulation
EXTV CC Switchover Voltage
6V < V IN < 38V
I CC = 0mA to 50mA
EXTV CC Rising
5.1
4.4
5.3
–1
4.6
5.55
–2
4.75
V
%
V
EXTV CC(HYS)
EXTV CC Switchover Hysteresis
200
mV
? EXTV CC
EXTV CC Voltage Drop
V EXTVCC = 5V, I CC = 50mA
200
mV
PGOOD Output
PGD OV
PGD UV
PGD HYS
V PGD(LO)
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
PGOOD Low Voltage
V FB Rising (with Respect to Regulated
Feedback Voltage V REG )
V FB Falling (with Respect to Regulated
Feedback Voltage V REG )
V FB Returning
I PGOOD = 5mA
5
–10
7.5
–7.5
2
0.15
10
–5
0.4
%
%
%
V
t PGD(FALL)
t PGD(RISE)
Delay from OV/UV Fault to PGOOD Falling
Delay from OV/UV Recovery to PGOOD
Rising
20
10
μs
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The junction temperature (T J in °C) is calculated from the ambient
temperature (T A in °C) and power dissipation (P D in Watts) as follows:
T J = T A + (P D ? θ JA )
where θ JA (in °C/W) is the package thermal impedance provided in the Pin
Configuration section for the corresponding package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3833 is tested under pulsed loading conditions such
that T J ≈ T A . The LTC3833E is guaranteed to meet specifications from
0°C to 85°C junction temperature; specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3833I is guaranteed to meet specifications over the full –40°C to 125°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance and other environmental factors.
Note 5: The LTC3833 is tested in a feedback loop that adjusts
V FB = V OSNS+ – V OSNS– to achieve a specified error amplifier output voltage
(on ITH pin). The specification at 85°C is not tested in production. This
specification is assured by design, characterization and correlation to
production testing at 125°C.
Note 6: Delay times are measured using 50% levels.
3833f
4
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