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| 型号： | LTC3834EUFD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 20-QFN |
| 标准包装： | 73 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 580kHz |
| 占空比： | 99.4% |
| 电源电压： | 4 V ~ 36 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3834
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3834 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET (TG)
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
external ?lter network connected to the PLLLPF pin. The
relationship between the voltage on the PLLLPF pin and
operating frequency, when there is a clock signal applied
to PLLIN/MODE, is shown in Figure 7 and speci?ed in the
Electrical Characteristics table. Note that the LTC3834 can
only be synchronized to an external clock whose frequency
is within range of the LTC3834’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simpli?ed block diagram
is shown in Figure 8.
900
800
700
If the external clock frequency is greater than the internal
oscillator’s frequency, f OSC , then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f OSC , current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ?lter capacitor C LP holds the voltage.
The loop ?lter components, C LP and R LP , smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The ?lter
components C LP and R LP determine how fast the loop
acquires lock. Typically R LP = 10k and C LP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
2.4V
R LP
C LP
600
500
400
300
EXTERNAL
OSCILLATOR
PLLIN/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLLPF
OSCILLATOR
200
100
0
0
0.5 1 1.5 2
2.5
3834 F08
PLLLPF PIN VOLTAGE (V)
3835 F07
Figure 8. Phase-Locked Loop Block Diagram
Figure 7. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
3834fb
19
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