参数资料
型号: LTC3859EFE#PBF
厂商: Linear Technology
文件页数: 32/42页
文件大小: 0K
描述: IC REG CTRLR BST PWM CM 38-TSSOP
标准包装: 50
PWM 型: 电流模式,Burst Mode?
输出数: 3
频率 - 最大: 850kHz
占空比: 100%
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 38-TFSOP (0.173",4.40mm 宽)裸露焊盘
包装: 管件
LTC3859
APPLICATIONS INFORMATION
The R SENSE resistor value can be calculated by using the
minimum value for the maximum current sense threshold
(43mV):
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
R SENSE ≤
43mV
6.88A
= 0.006 Ω
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
Choosing 1% resistors: R A = 25k and R B = 80.6k yields
an output voltage of 3.33V.
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R DS(ON) = 0.035Ω/0.022Ω, C MILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
synchronous buck regulators operating in the continuous
mode. Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at C IN ? Do not attempt to split the input
decoupling for the two channels as it can cause a large
P MAIN =
3.3V
22V
(6A) 2 { 1 + (0.005)(50 ° C ? 25 ° C) }
resonant loop.
2. Are the signal and power grounds kept separate?
(0.035 Ω ) + (22V) 2 6
5A
2
(2.5 Ω )(215pF) ?
The combined IC signal ground pin and the ground
return of C INTVCC must return to the combined C OUT
?
? 5V ? 2.3V
? (350kHz) = 433mW
?
1
+
1 ?
2.3V ?
(–) terminals. The path formed by the top N-channel
MOSFET, Schottky diode and the C IN capacitor should
have short leads and PC trace lengths. The output
I SC =
? ?
? = 3.07A
A  short-circuit  to  ground  will  result  in  a  folded  back
current of:
20 mV 1 ? 95ns(22V) ?
0.006 Ω 2 ? 3.9μH ?
with a typical value of R DS(ON) and z = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
P SYNC = (2.23A) 2 (1.125)(0.022 Ω ) = 233mW
which is less than under full-load conditions.
The input capacitor to the buck regulator C IN is chosen
for an RMS current rating of at least 3A at temperature
assuming only this channel is on. C OUT is chosen with
an ESR of 0.02Ω for low output ripple. The output ripple
in continuous mode will be highest at the maximum
input voltage. The output voltage ripple due to ESR is
approximately:
V ORIPPLE = R ESR ( D I L ) = 0.02Ω(1.75A) = 35mV P-P
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
3. Do the LTC3859 V FB pins’ resistive dividers connect to
the (+) terminals of C OUT ? The resistive divider must be
connected between the (+) terminal of C OUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The ?lter capacitor between
SENSE + and SENSE – should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV CC decoupling capacitor connected close
to the IC, between the INTV CC and the power ground
pins? This capacitor carries the MOSFET drivers’ current
peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV CC and PGND pins can
help improve noise performance substantially.
3859fa
32
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