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参数资料
| 型号： | LTC3862IUH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/42页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 24-QFN |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 96% |
| 电源电压： | 4 V ~ 36 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 24-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3862
OPERATION
Operation at High Supply Voltage
At high input voltages, the LTC3862’s internal LDO can
dissipate a significant amount of power, which could
cause the maximum junction temperature to be exceeded.
Conditions such as a high operating frequency, or the use
of more than one power MOSFET per channel, could push
the junction temperature rise to high levels. If the thermal
equations above indicate too high a rise in the junction
temperature, an external bias supply can always be used
to reduce the power dissipation on the IC, as shown in
Figure 3.
For example, a 5V or 12V system rail that is available
would be more suitable than the 24V main input power
rail to power the LTC3862. Also, the bias power can be
generated with a separate switching or LDO regulator. An
example of an LDO regulator is shown in Figure 3. The
output voltage of the LDO regulator can be set by selecting
an appropriate Zener diode to be higher than 5V but low
enough to divide the power dissipation between LTC3862
and Q1 in Figure 3. The absolute maximum voltage rating
of the INTV CC pin is 6V.
flow from the external INTV CC supply, through the body
diode of the LDO PMOS device, to the input capacitor
and V IN pin. This high current flow could trigger a latchup
condition and cause catastrophic failure of the IC.
If, however, the V IN supply to the IC comes up before the
INTV CC supply, the external INTV CC supply will act as a
load to the internal LDO in the LTC3862, and the LDO will
attempt to charge the INTV CC output with its short-circuit
current. This will result in excessive power dissipation and
possible thermal overload of the LTC3862.
If an independent 5V supply exists in the system, it may be
possible to short INTV CC and V IN together to 5V in order
to reduce gate drive power dissipation. With V IN and INT-
V CC shorted together, the LDO output PMOS transistor is
biased at V DS = 0V, and the current demand of the internal
analog and digital control circuitry, as well as the gate
drive current, will be supplied by the external 5V supply.
Programming the Output Voltage
The output voltage is set by a resistor divider according
to the following formula:
V OUT = 1 . 223 V ? 1 +
V IN
?
?
R2 ?
R 1 ? ?
R1
Q1
D1 V IN
(OPT) LTC3862
INTV CC
C VCC 3862 F03
Figure 3. Using the LTC3862 with an External Bias Supply
Power Supply Sequencing
As shown in Figure 1, there are body diodes in parallel
with the PMOS output transistors in the two LDO regula-
tors in the LTC3862. As a result, it is not possible to bias
the INTV CC and V IN pins of the chip from separate power
supplies. Independently biasing the INTV CC pin from a
separate power supply can cause one of two possible
failure modes during supply sequencing. If the INTV CC
supply comes up before the V IN supply, high current will
The external resistor divider is connected to the output as
shown in Figure 4. Resistor R1 is normally chosen so that
the output voltage error caused by the current flowing out of
the V FB pin during normal operation is negligible compared
to the current in the divider. For an output voltage error
due to the error amp input bias current of less than 0.5%,
this translates to a maximum value of R1 of about 30k.
V OUT
LTC3862 R2
FB
R1
SGND
3862 F04
Figure 4. Programming the Output Voltage
with a Resistor Divider
3862fc
For more information www.linear.com/LTC3862
15
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