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参数资料
| 型号： | LTC3862IUH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/42页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 24-QFN |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 96% |
| 电源电压： | 4 V ~ 36 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 24-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3862
PIN FUNCTIONS
(SSOP/QFN/TSSOP)
3V8 (Pin 24/Pin 22/Pin 24): Output of the Internal 3.8V
LDO from INTV CC . Supply pin for the low voltage analog
and digital circuits. A low ESR 1nF ceramic bypass capacitor
should be connected between 3V8 and SGND, as close
as possible to the IC.
BLANK (Pin 3/Pin 1/Pin 3): Blanking Time. Floating this
pin provides a nominal minimum on-time of 260ns. Con-
necting this pin to 3V8 provides a minimum on-time of
340ns, while connecting it to SGND provides a minimum
on-time of 180ns.
CLKOUT (Pin 10/Pin 8/Pin 10): Digital Output Used for
Daisy-Chaining Multiple LTC3862 ICs in Multi-Phase
Systems. The PHASEMODE pin voltage controls the
relationship between CH1 and CH2 as well as between
CH1 and CLKOUT.
D MAX (Pin 1/Pin 23/Pin 1): Maximum Duty Cycle. This pin
programs the maximum duty cycle. Floating this pin pro-
vides 84% duty cycle. Connecting this pin to 3V8 provides
75% duty cycle, while connecting it to SGND provides 96%
duty cycle. The maximum duty cycle is derived from an
internal clock that runs at 12x the programmed switching
frequency. As a result, the maximum duty cycle limit D MAX
is extremely precise.
FB (Pin 8/Pin 6/Pin 8): Error Amplifier Input. The FB pin
should be connected through a resistive divider network
to V OUT to set the output voltage.
FREQ (Pin 5/Pin 3/Pin 5): A resistor from FREQ to SGND
sets the operating frequency.
GATE1 (Pin 18/Pin 16/Pin 18): Gate Drive Output. The
LTC3862 provides a 5V gate drive referenced to PGND to
drive a logic-level threshold MOSFET. The gate pin is rated
for an absolute maximum voltage of –0.3V minimum and
6V maximum.
GATE2 (Pin 16/Pin 14/Pin 16): Gate Drive Output. The
LTC3862 provides a 5V gate drive referenced to PGND to
drive a logic-level threshold MOSFET. The gate pin is rated
for an absolute maximum voltage of –0.3V minimum and
6V maximum.
INTV CC (Pin 19/Pin 17/Pin 19): Output of the Internal 5V
Low Dropout Regulator (LDO). A low ESR 4.7μF (X5R or
better) ceramic bypass capacitor should be connected
between INTV CC and PGND, as close as possible to the IC.
ITH (Pin 7/Pin 5/Pin 7): Error Amplifier Output. The current
comparator trip threshold increases with the ITH control
voltage. The ITH pin is also used for compensating the
control loop of the converter.
PGND (Pin 17/Pin 15, Exposed Pad Pin 25/Pin 17,
Exposed Pad Pin 25): Power Ground. Connect this pin
close to the sources of the power MOSFETs. PGND should
also be connected to the negative terminals of V IN and
INTV CC bypass capacitors. PGND is electrically isolated
from the SGND pin. The Exposed Pad of the FE and QFN
packages is connected to PGND and must be soldered
to PCB ground for electrical contact and rated thermal
performance.
PHASEMODE (Pin 4/Pin 2/Pin 4): The PHASEMODE pin
voltage programs the phase relationship between CH1 and
CH2 rising gate signals, as well as the phase relationship
between CH1 gate signal and CLKOUT. Floating this pin or
connecting it to either 3V8, or SGND changes the phase
relationship between CH1, CH2 and CLKOUT.
PLLFLTR (Pin 12/Pin 10/Pin 12): PLL Lowpass Filter Input.
When synchronizing to an external clock, this pin serves as
the lowpass filter input for the PLL. A series resistor and
capacitor connected from PLLFLTR to SGND compensate
the PLL feedback loop.
RUN (Pin 21/Pin 19/Pin 21): Run Control Input. A voltage
above 1.22V on the pin turns on the IC. Forcing the pin
below 1.22V causes the IC to shut down. There is a 0.5μA
pull-up current for this pin. Once the RUN pin raises above
1.22V, an additional 4.5μA pull-up current is added to the
pin for programmable hysteresis.
SENSE1 + (Pin 23/Pin 21/Pin 23): Positive Inputs to the
Current Comparators. The ITH pin voltage programs the
current comparator offset in order to set the peak current
trip threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.
3862fc
For more information www.linear.com/LTC3862
9
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