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参数资料
| 型号： | LTC3873ITS8-5#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST FLYBK TSOT23-8 |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 240kHz |
| 占空比： | 84% |
| 电源电压： | 4 V ~ 75 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 包装： | 带卷 (TR) |
LTC3873-5
APPLICATIONS INFORMATION
Turns Ratios
Due to the use of the external feedback resistor divider
ratio to set output voltage, the user has relative freedom
in selecting a transformer turns ratio to suit a given ap-
plication. Simple ratios of small integers, e.g., 1:1, 2:1, 3:2,
etc. can be employed which yield more freedom in setting
total turns and mutual inductance. Simple integer turns
ratios also facilitate the use of “off-the-shelf” con?gurable
transformers such as the Coiltronics VERSA-PAC series
in applications with high input to output voltage ratios.
For example, if a 6-winding VERSA-PAC is used with three
windings in series on the primary and three windings in
parallel on the secondary, a 3:1 turns ratio will be achieved.
Turns ratio can be chosen on the basis of desired duty
cycle. However, remember that the input supply voltage
plus the secondary-to-primary referred version of the
?yback pulse (including leakage spike) must not exceed
the allowed external MOSFET breakdown rating.
Leakage Inductance
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
output switch (Q1) turn-off. This is increasingly prominent
at higher load currents where more stored energy must
be dissipated. In some cases a “snubber” circuit will be
required to avoid overvoltage breakdown at the MOSFET’s
drain node. Application Note 19 is a good reference on
snubber design. A bi?lar or similar winding technique is a
and gate-to-drain charges (Q GS and Q GD , respectively),
the maximum drain current (I D(MAX) ) and the MOSFET’s
thermal resistances (R TH(JC) and R TH(JA) ).
Current Limit Programming
During the switch on-time, the control circuit limits the
maximum voltage drop across the current sense com-
ponent to about 270mV, 100mV and 170mV at low duty
cycle with IPRG tied to V IN , GND or left ?oating respec-
tively. For boost applications with R DS(ON) sensing, refer
to the LTC3872 data sheet for the selection of MOSFET
R DS(ON) .
MOSFETs have conduction losses (I 2 R) and switching
losses. For V DS < 20V, high current ef?ciency generally
improves with large MOSFETs with low R DS(ON) , while
for V DS > 20V the transition losses rapidly increase to the
point that the use of a higher R DS(ON) device with lower
reverse transfer capacitance, C RSS , actually provides
higher ef?ciency.
Output Capacitors
The output capacitor is normally chosen by its effective
series resistance (ESR), which determines output ripple
voltage and affects ef?ciency. Low ESR ceramic capaci-
tors are often used to minimize the output ripple. Boost
regulators have large RMS ripple current in the output
capacitor that must be rated to handle the current. The
output ripple current (RMS) is:
good way to minimize troublesome leakage inductances.
However, remember that this will limit the primary-to-
secondary breakdown voltage, so bi?lar winding is not
I RMS ( COUT ) ≈ I OUT ( MAX ) ?
V OUT – V IN ( MIN )
V IN ( MIN )
always practical.
Power MOSFET Selection
The power MOSFET serves two purposes in the LTC3873-5:
it represents the main switching element in the power path
and its R DS(ON) represents the current sensing element
Output ripple is then simply:
V OUT = R ESR ( Δ I L(RMS) )
The output capacitor for ?yback converter should have a
ripple current rating greater than:
for the control loop. Important parameters for the power
MOSFET include the drain-to-source breakdown voltage
(BV DSS ), the threshold voltage (V GS(TH) ), the on-resistance
I RMS = I OUT ?
D MAX
1 – D MAX
(R DS(ON) ) versus gate-to-source voltage, the gate-to-source
38735fb
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