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参数资料
| 型号： | LTC3876IUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 36/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-QFN |
| 标准包装： | 52 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
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LTC3876
APPLICATIONS INFORMATION
VDDQ = 0 . 6 V 1 + FB 2
sourcewillscaletheV IN currentrequiredforthedriver
and controller circuits by a factor of (duty cycle)/(ef-
ficiency). For example, in a 20V to 5V application, 10mA
of DRV CC current results in approximately 2.5mA of V IN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from V IN )
to only a few percent.
4. C IN loss. The input capacitor filters large square-wave
input current drawn by the regulator into an averaged
DC current from the supply. The capacitor itself has
a zero average DC current, but square-wave-like AC
current flows through it. Therefore the input capacitor
must have a very low ESR to minimize the RMS current
loss on ESR. It must also have sufficient capacitance
to filter out the AC component of the input current to
prevent additional RMS losses in upstream cabling,
fuses or batteries. The LTC3876 2-phase architecture
improves the ESR loss.
“Hidden” copper trace, fuse and battery resistance, even
at DC current, can cause a significant amount of efficiency
degradation, so it is important to consider them during
VDDQ at 20A, a 0.75V VTT 10A maximum average operat-
ing current with a VTT reference output (VTTR) capable of
supplying up to ±50mA. (see Figure 11, LTC3876 demo
circuit 1631A)
The regulated channel 1 VDDQ output supply voltage is
determined by:
? R ?
? R FB 1 ?
Set VDDQ to 1.5V for DDRIII application. Using a 20k
resistor for R FB1 , the resulting R BF2 is 30k.
The regulated channel 2 VTT termination supply is differ-
entially referenced to an internal resistor divider connected
between the VDDQSNS and the V OUTSENSE– . The resulting
differential VTT reference output (VTTR) is one-half VDDQ
which in this design example is 0.75V. The VTT termina-
tion supply nominally regulates to 0.75V and will track
any dynamic movement of the channel 1 VDDQ supply.
The switching frequency for both channels is programmed
by:
the design phase. Other losses, which include the C OUT
ESR loss, bottom MOSFET ’s body diode reverse-recovery
loss, and inductor core loss generally account for less
R T [ kΩ ] = 4 ?
41 5 50
f [ kHz ]
– 2 . 2
than 2% additional loss.
Power losses in the switching regulator will reflect as
a higher than ideal duty cycle, or a longer on-time for a
constant frequency. This efficiency accounted on-time
can be calculated as:
t ON ≈ t ON(IDEAL) /Efficiency
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased.
Design Example
The following design example is the DDR3 application
circuit as implemented on the standard LTC3876 QFN
demo board 1631A. This DC/DC step-down converter
design accommodates an input V IN range of 4.5V to 14V,
with a VDDQ output of 1.5V and a VTT output of 0.75V.
The DDRIII output channels are designed to produce 1.5V
For f = 400kHz, R T = 102kΩ.
The minimum on-time occurs for maximum V IN and
should be greater than the typical minimum of 30ns with
adequate margin. The minimum on-time margin should
allow for device variability and the extension of effective
on-time at light load due to the dead times. The reason
for the on-time extension at light load is that the negative
inductor current causes the switch node to rise which
effectively adds to the on time. This is of limited concern
to the channel 1 VDDQ but is of greater concern to the
channel 2 VTT supply because it supplies significant
negative current. For the LTC3876 the minimum on-time
without any extension is 30ns, with driver dead times of
30ns. For strong negative currents in VTT the total dead
time is the total of the minimum on-time, plus both dead
times for 90ns. It is therefore recommended to keep the
minimum on-time greater than 100ns for channel 2 VTT
to assure PLL lock under all operating conditions.
3876f
36
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相关代理商/技术参数 |
参数描述 |
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| LTC3878EGN#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
| LTC3878EGN#PBF | 制造商:Linear Technology 功能描述:IC SYNC STEP-DOWN REGULATOR CTRL SSOP-16 |
| LTC3878EGN#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LTC3878IGN#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LTC3878IGN#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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