参数资料
型号: LTC4059EDC#TRMPBF
厂商: Linear Technology
文件页数: 9/12页
文件大小: 0K
描述: IC BATT CHARGER LI-ION REG 6DFN
标准包装: 500
功能: 充电管理
电池化学: 锂离子(Li-Ion)
电源电压: 3.75 V ~ 8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN 裸露焊盘
供应商设备封装: 6-DFN-EP(2x2)
包装: 带卷 (TR)
其它名称: LTC4059EDC#PBF
LTC4059EDC#PBF-ND
LTC4059/LTC4059A
APPLICATIO S I FOR ATIO
115 ° C – T A
( V CC BAT JA
) ? θ
I BAT =
=
Power Dissipation
The conditions that cause the LTC4059/LTC4059A to
reduce charge current through thermal feedback can be
approximated by considering the power dissipated in the
IC. For high charge currents, the LTC4059 power dissipa-
tion is approximately:
P D = (V CC – V BAT ) ? I BAT
where P D is the power dissipated, V CC is the input supply
voltage, V BAT is the battery voltage and I BAT is the charge
current. It is not necessary to perform any worst-case
power dissipation scenarios because the LTC4059/
LTC4059A will automatically reduce the charge current to
maintain the die temperature at approximately 115 ° C.
However, the approximate ambient temperature at which
the thermal feedback begins to protect the IC is:
T A = 115 ° C – P D θ JA
T A = 115 ° C – (V CC – V BAT ) ? I BAT ? θ JA
Example: Consider an LTC4059 operating from a 5V wall
adapter providing 900mA to a 3.7V Li-Ion battery. The
ambient temperature above which the LTC4059/LTC4059A
begin to reduce the 900mA charge current is approximately:
T A = 115 ° C – (5V – 3.7V) ? (900mA) ? 50 ° C/W
T A = 115 ° C – 1.17W ? 50 ° C/W = 115 ° C – 59 ° C
T A = 56 ° C
The LTC4059 can be used above 56 ° C, but the charge
current will be reduced from 900mA. The approximate
current at a given ambient temperature can be calculated:
I BAT =
– V
Using the previous example with an ambient temperature
of 65 ° C, the charge current will be reduced to approximately:
115 ° C – 65 ° C 50 ° C
( 5 V – 3 . 7 V ) ? 50 ° C / W 65 ° C / A
I BAT = 770 mA
Furthermore, the voltage at the PROG pin will change
proportionally with the charge current as discussed in the
Programming Charge Current section.
It is important to remember that LTC4059/LTC4059A
applications do not need to be designed for worst-case
thermal conditions since the IC will automatically reduce
power dissipation when the junction temperature reaches
approximately 115 ° C.
Board Layout Considerations
In order to be able to deliver maximum charge current
under all conditions, it is critical that the exposed metal
pad on the backside of the LTC4059/LTC4059A package is
soldered to the PC board ground. Correctly soldered to a
2500mm 2 double sided 1oz copper board the LTC4059/
LTC4059A have a thermal resistance of approximately
60 ° C/W. Failure to make thermal contact between the
exposed pad on the backside of the package and the
copper board will result in thermal resistances far greater
than 60 ° C/W. As an example, a correctly soldered LTC4059/
LTC4059A can deliver over 900mA to a battery from a 5V
supply at room temperature. Without a backside thermal
connection, this number could drop to less than 500mA.
Stability Considerations
The LTC4059 contains two control loops: constant voltage
and constant current. The constant-voltage loop is stable
without any compensation when a battery is connected
with low impedance leads. Excessive lead length, how-
ever, may add enough series inductance to require a
bypass capacitor of at least 1 μ F from BAT to GND. Further-
more, a 4.7 μ F capacitor with a 0.2 ? to 1 ? series resistor
from BAT to GND is required to keep ripple voltage low
when the battery is disconnected.
High value capacitors with very low ESR (especially ce-
ramic) reduce the constant-voltage loop phase margin.
Ceramic capacitors up to 22 μ F may be used in parallel with
a battery, but larger ceramics should be decoupled with
0.2 ? to 1 ? of series resistance.
In constant-current mode, the PROG pin is in the feedback
loop, not the battery. Because of the additional pole
created by PROG pin capacitance, capacitance on this pin
must be kept to a minimum. With no additional capaci-
tance on the PROG pin, the charger is stable with program
resistor values as high as 12k. However, additional ca-
pacitance on this node reduces the maximum allowed
4059fb
9
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