参数资料
| 型号： | LTC4213CDDB#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC CIRC BREAK ELEC 8-DFN |
| 标准包装： | 500 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（3x2） |
| 包装： | 带卷 (TR) |
LTC4213
11
4213f
supply transient dips below 1.97V of less than 80s are
ignored.
ON Function
When VON is below comparator COMP1’s threshold of
0.4V for 80s, the device resets. The system leaves reset
mode if the ON pin rises above comparator COMP2’s
threshold of 0.8V and the UVLO condition is met. Leaving
reset mode, the GATE pin starts up after a tDEBOUNCE delay
of 60s. When ON goes below 0.76V, the GATE shuts off
after a 5s glitch filter delay. The output is discharged by
the external load when VON is in between 0.4V to 0.8V. At
this state, the ON pin can re-enable the GATE if VON
exceeds 0.8V for more than 8s. Alternatively, the device
resets if the ON pin is brought below 0.4V for 80s. Once
reset, the GATE pin restarts only after the tDEBOUNCE 60s
delay at VON rising above 0.8V. To protect the ON pin from
overvoltage stress due to supply transients, a series
resistor of greater than 10k is recommended when the ON
pin is connected directly to the supply. An external resis-
tive divider at the ON pin can be used with COMP2 to set
a supply undervoltage lockout value higher than the inter-
nal UVLO circuit. An RC filter can be implemented at the
ON pin to increase the powerup delay time beyond the
internal 60s delay.
Gate Function
The GATE pin is held low in reset mode. 60s after leaving
reset mode, the GATE pin is charged up by an internal
100A current source. The circuit breaker arms when
VGATE > VSENSEN + VGSARM. In normal mode operation,
the GATE peak voltage is internally clamped to VGSMAX
above the SENSEN pin. When the circuit breaker trips, an
internal MOSFET shorts the GATE pin to GND, turning off
the external MOSFET.
READY Status
The READY pin is held low during reset and at startup. It
is pulled high by an external pullup resistor 50s after the
circuit breaker arms. The READY pin pulls low if the circuit
breaker trips or the ON pin is pulled below 0.76V, or VCC
drops below undervoltage lockout.
VGSARM and VGSMAX
Each MOSFET has a recommended VGS drive voltage
where the channel is deemed fully enhanced and RDSON is
minimized. Driving beyond this recommended VGS volt-
age yields a marginal decrease in RDSON. At startup, the
gate voltage starts at ground potential. The GATE ramps
past the MOSFET threshold and the load current begins to
flow. When VGS exceeds VGSARM, the circuit breaker is
armed and enabled. The chosen MOSFET should have a
recommended minimum VGS drive level that is lower than
VGSARM. Finally, VGS reaches a maximum at VGSMAX.
Trip and Reset Circuit Breaker
Figure 2 shows the timing diagram of VGATE and VREADY
after a fault condition. A tripped circuit breaker can be reset
either by cycling the VCC bias supply below UVLO thresh-
old or pulling ON below 0.4V for >tRESET. Figure 3 shows
the timing diagram for a tripped circuit breaker being reset
by the ON pin.
Calculating Current Limit
The fault current limit is determined by the RDSON of the
MOSFET and the circuit breaker voltage VCB.
I
V
R
LIMIT
CB
DSON
=
()
2
The RDSON value depends on the manufacturer’s distribu-
tion, VGS and junction temperature. Short Kelvin-sense
connections between the MOSFET drain and source to
the LTC4213 SENSEP and SENSEN pins are strongly
recommended.
For a selected MOSFET, the nominal load limit current is
given by:
I
V
R
LIMIT NOM
CB NOM
DSON NOM
()
=
3
The minimum load limit current is given by:
I
V
R
LIMIT MIN
CB MIN
DSON MAX
()
=
4
APPLICATIO S I FOR ATIO
WU
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