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参数资料
| 型号： | LTC4214-1IMS#TR |
| 厂商： | Linear Technology |
| 文件页数： | 14/32页 |
| 文件大小： | 277K |
| 描述： | IC CTRLR HOTSWAP NEG LV 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 6 V ~ 16 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
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LTC4214-1/LTC4214-2
14
421412f
UV/OV OPERATION
A low input to the UV comparator will reset the LTC4214
and pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4214,
pulls the MOSFET gate low and resets the latched PWRGD
high.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
DRAIN
Connecting an external resistor, R
D
, to the dual function
DRAIN pin allows V
OUT
sensing without it being damaged
by large voltage transients. Below 3V, negligible pin leak-
age allows a DRAIN low comparator to detect V
OUT
less
than 1.232V (V
DRNL
). This condition, together with the
GATE low comparator, sets the PWRGD flag.
If V
OUT
> V
DRNCL
(4.2V), the DRAIN pin is clamped at about
4.2V and the current flowing in R
D
is given by:
I
V
V
R
DRN
OUT
DRNCL
D
H
(1)
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 40礎 TIMER current. This
accelerates the fault TIMER pull-up when the MOSFETs
drain-source voltage exceeds 4.2V and effectively short-
ens the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C
T
is used at
TIMER to provide timing for the LTC4214. Four different
charging and discharging modes are available at TIMER:
1) A 5礎 slow charge; initial timing and shutdown cooling
delay.
2) A (40礎 + 8 " I
DRN
) fast charge; circuit breaker delay.
3) A 5礎 slow discharge; circuit breaker "cool off" and
shutdown cooling.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5礎 pull-up is used. The low
impedance switch is turned off and the 5礎 current source
is enabled when the interlock conditions are met. C
T
charges to 3V in a time period given by:
V C
A
T
=
3
5
"
(2)
When C
T
reaches 3V (V
TMRH
), the low impedance switch
turns on and discharges C
T
. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
R
S
, the TIMER pin charges C
T
with (40礎 + 8 " I
DRN
). If C
T
charges to 3V, the GATE pin pulls low and the LTC4214-1
latches off while the LTC4214-2 starts a shutdown cooling
cycle. The LTC4214-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or V
IN
dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
t
V C
A
I
T
DRN
=
?nbsp +
3
40
8
"
"
(3)
If V
OUT
< 3V, an internal PMOS device isolates any DRAIN
pin leakage current, making I
DRN
= 0礎 in Equation (3). If
V
OUT
> 4.2V (V
DRNCL
) during the circuit breaker fault period,
the charging of C
T
accelerates by 8 " I
DRN
of Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
will not reach 3V and the LTC4214 will not shut the external
APPLICATIO S I FOR ATIO
U
U
U
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