参数资料
型号: LTC4214-1IMS#TR
厂商: Linear Technology
文件页数: 9/32页
文件大小: 277K
描述: IC CTRLR HOTSWAP NEG LV 10MSOP
标准包装: 2,500
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 6 V ~ 16 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 带卷 (TR)
LTC4214-1/LTC4214-2
9
421412f
UV (Pin 9): Undervoltage Input. The active high threshold
at the UV pin is set at 2.25V with respect to V
EE
 and exhibits
0.25V hysteresis. If UV < 2V, PWRGD pulls high, both
GATE and TIMER pull low. If UV rises above 2.25V, this
initiates an initial timing cycle followed by GATE start-up.
The internal UVLO at V
IN
 always overrides UV. A low at UV
resets an internal fault latch. A 1nF to 10nF capacitor at UV
prevents transients and switching noise from affecting the
UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 10): Timer Input. TIMER is used to generate
an initial timing delay at start-up and to delay shutdown in
the event of an output overload (circuit breaker fault).
TIMER starts an initial timing cycle when the following
conditions are met: UV is high, OV is low, V
IN
 clears UVLO,
TIMER pin is low, GATE is lower than V
GATEL
, SS < 0.2V,
and V
SENSE
  V
EE
 < V
CB
. A pull-up current of 5礎 then
charges C
T
, generating a time delay. If C
T
 charges to
V
TMRH
 (3V), the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 40礎 pull-up current charging
C
T
. If DRAIN is approximately 4.2V during this cycle, the
timer pull-up has an additional current of 8 " I
DRN
. If SENSE
drops below 50mV before TIMER reaches 3V, a 5礎 pull-
down current slowly discharges the C
T
. In the event that C
T
eventually integrates up to the V
TMRH
 threshold, the circuit
breaker trips, GATE quickly pulls low and PWRGD pulls
high. The LTC4214-1 TIMER pin latches high with a 5礎
pull-up source. This latched fault is cleared by either
pulling TIMER low with an external device or by pulling UV
below 2V. The LTC4214-2 starts a shutdown cooling cycle
following an overcurrent fault. This cycle consists of 4
discharging ramps and 3 charging ramps. The charging
and discharging currents are 5礎 and TIMER ramps
between its 1.7V and 3V thresholds. At the completion of
a shutdown cooling cycle, the LTC4214-2 attempts a start-
up cycle.
PI   FU CTIO S
U
U
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