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参数资料
| 型号： | LTC4215CUFD-2#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/28页 |
| 文件大小： | 265K |
| 描述： | IC CTRLR HOT SWAP 24-QFN |
| 标准包装： | 73 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.9 V ~ 15 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 管件 |
| 产品目录页面： | 1342 (CN2011-ZH PDF) |
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LTC4215/LTC4215-2
13
4215fe
APPLICATIONS INFORMATION
dI/dt ramp stops and the inrush current follows the foldback
pro le as shown in Figure 2. The TIMER pin integrates at
100糀 during start-up and once it reaches its threshold
of 1.235V , the part checks to see if it is in current limit,
which indicates that it has started up into a short-circuit
condition. If this is the case, the overcurrent fault bit, D2
in Table 5, is set and the part turns off. If the part is not in
current limit, the 25mV circuit breaker is armed and the
current limit is switched to 75mV . Alternately an internal
100ms start-up timer may be selected by tying the TIMER
pin to INTV
CC
.
As the SOURCE voltage rises, the FB pin follows as set
by R7 and R8. Once FB crosses its 1.235V threshold, and
the start-up timer has expired, the GPIO pin, in its default
con guration, ceases to pull low and indicates that power
is now good.
generates an OC fault, or the FB pin voltage crosses its
1.235V power good threshold and the GPIO pin signals
power good.
GATE Pin Voltage
A curve of GATE-to-SOURCE drive vs V
DD
is shown in the
Typical Performance Characteristics. At minimum input
supply voltage of 2.9V , the minimum GATE-to-SOURCE
drive voltage is 4.7V . The GATE-to-SOURCE voltage is
clamped below 6.5V to protect the gates of logic level
N-channel MOSFETs.
Turn-Off Sequence
The GATE is turned off by a variety of conditions. A normal
turn-off is initiated by the ON pin going low or a serial bus
turn-off command. Additionally, several fault conditions
turn off the GATE. These include an input overvoltage
(OV pin), input undervoltage (UV pin), overcurrent circuit
breaker (SENSE
pin), or EN transitioning high. Writing
a logic one into the UV , OV or OC fault bits (D0-D2 in
Table 5) also latches off the GATE if their auto-retry bits
are set to false.
Normally the MOSFET is turned off with a 1mA current
pulling down the GATE pin to ground. With the MOSFET
turned off, the SOURCE and FB voltages drop as C
L
dis-
charges. When the FB voltage crosses below its threshold,
GPIO pulls low to indicate that the output power is no
longer good.
If the V
DD
pin falls below 2.74V for greater than 2約 or
INTV
CC
drops below 2.60V for greater than 1約, a fast shut
down of the MOSFET is initiated. The GATE pin is pulled
down with a 450mA current to the SOURCE pin.
Overcurrent Fault
The LTC4215 features an adjustable current limit that
protects against short circuits or excessive load current.
An overcurrent fault occurs when the circuit breaker 25mV
threshold has been exceeded for longer than the 20約
(LTC4215) or 420約 (LTC4215-2) time-out delay. Current
limiting begins immediately when the current sense voltage
between the V
DD
and SENSE pins reaches 75mV . The GATE
V
DD
+ 6V
V
GATE
V
OUT
GPIO1
(POWER GOOD)
I
LOAD
" R
SENSE
V
DD
V
SENSE
25mV
10mV
SS
LIMITED
FB
LIMITED
4215 F02
TIMER
EXPIRES
t
STARTUP
Figure 2. Power-Up Waveforms
If R6 and C1 are employed for a constant current during
start-up, which produces a constant dV/dt at the output,
a 20糀 pull-up current from the gate pin slews the gate
upwards and the part is not in current limit. The start-up
TIMER may expire in this condition and an OC fault is not
generated even though start-up has not completed. Either
the sense voltage increases to the 25mV CB threshold and
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